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1MODULE-5Registers and Counters

2Books Referred Text Book: Donald P Leach, Albert Paul Malvino & Goutam Saha: DigitalPrinciples and Applications, 7th Edition, Tata McGraw Hill,2015 Reference Books: Anil K. Maini: Digital Electronics Principles, Devices andApplications, 2007, John Wiley & Sons, Ltd. Thomas L. Floyd: Digital Fundamentals, 9th Edition., PearsonInternational Edition. M. Morris Mano, Michael D. Ciletti : Digital Design With anIntroduction to the Verilog HDL, 5th Edition, PearsonEducation, Inc

3Objective Register Understand serial in-serial out shift registers and be familiar with the basic features of the 74LS91 registerUnderstand serial in-parallel out shift registers and be familiar with the basic features of the 74164registerUnderstand parallel in-serial out shift registers and be familiar with the basic features of the 74166registerUnderstand parallel in-parallel out shift registers and be familiar with the basic features of the74174 and 7495A registersUnderstand working of Universal shift register with the basic features of the 74194 register.State various uses of shift registers Counter Describe the basic construction and operation of an asynchronous counter Determine the logic circuit needed to decode a given state from the output of a given counter Describe the synchronous counter and its advantages See how the modulus of a counter can be reduced by skipping one or more of its natural counts


5Introduction A register is simply a group of flip-flops that can be used to store a binarynumber. There must be one flip-flop for each bit in the binary number. A register is a digital circuit with two basic functions: data storage anddata movement. E.g. a register used to store an 8-bit binary number must have eight flip-flops. Naturally the flip-flops must be connected such that the binary numbercan be entered (shifted) into the register and possibly shifted out. A group of flip-flops connected to provide either or both of these functions is called ashift register. Applications: A data register is often used to momentarily store binary information e.g. RAM. A register used in a microprocessor chip. E.g. Processor Register Shift Register is a sequence generator and sequence detector and also as parallel toserial converters offers very distinct advantages.

6TYPES OF REGISTERS-1 The bits in a binary number can be moved from one place to another in either of two ways.The first method involves shifting the data 1 bit at a time in a serialfashion, beginning with either the most significant bit (MSB) or the leastsignificant bit (LSB). This technique is referred to as serial shifting.The second method involves shifting all the data bits simultaneously andis referred to as parallel shifting.There are two ways to shift data into a register (serial or parallel) andsimilarly two ways to shift the data out of the register.This leads to the construction of four basic register types: Serial-in-serial out (SISO) 54/74LS91, 8 bits Serial in-parallel out (SIPO) 54/74164, 8 bits Parallel in-serial out (PISO) 54/74165, 8 bits Parallel in-parallel out (PIPO) 54/74198, 8 bits




10SERIAL IN-SERIAL OUT-1 The flip-flops used to construct registers are usually edge-triggeredJK, SR or D types. D flip-flops connected as shown in figure forming 4-bit shift register.A common clock provides trigger at its negative edge to all the flipflops. As output of one D flip-flop is connected to input of the next at everyClock trigger data stored in one flip-flop is transferred to the next. For this circuit transfer takes place like this Q R, R S, S Tand serial data input is transferred to Q.


12SERIAL IN-SERIAL OUT-2 At clock edge A, D 0 Q, Q R, R S, S T When clock triggers, these inputsget transferred to correspondingflip-flop outputs simultaneouslyso that QRST 0000. Thus at clock trigger, values atDQRS is transferred to QRST.

13SERIAL IN-SERIAL OUT-3 At clock edge B, serial data in D 0, i.e.DQRS 0000. So after NT at B, QRST 0000. Serial data becomes 1 in next clockcycle. At clock edge C, DQRS 1000 and afterNT QRST 1000. Serial data goes to 0 in next clock cycle At clock edge D, DQRS 0100 and afterNT QRST 0100.

14SERIAL IN-SERIAL OUT-4 Example: Show how a number 0100 is entered serially in a 4-bit shiftregister using D flip-flop. Also write state table.

15SERIAL IN-SERIAL OUT-5 Example: Suppose that it has the 4-bit number QRST 1010stored in it so draw the waveformClkSerial InQRST00101010010120001030000100004

16SERIAL IN-SERIAL OUT-6 Example: 1010 Serial Input Entering serially into register

17SERIAL IN-SERIAL OUT-7 Example: 1010 Serial Input Entering serially into register

18SERIAL IN-SERIAL OUT-8 Example Data In 1001


20SERIAL IN-SERIAL OUT-10 74LS91 8-bit shift register The data input is applied at either A (pin 10) or B (pin 12). Notice that a data level at A ( orB) is complemented by the NAND gate and then applied to the R input of the first flip-flop. The same data level is complemented by the NAND gate and then complemented again bythe inverter before it appears at the S input. So, a 1 at input A will set the first flip-flop (inother words, this 1 is shifted into the first flip-flop) on a positive clock transition. The NAND gate with inputs A and B simply provides a gating function for the input datastream if desired. If gating is not desired, simply connect pins 10 and 12 together and apply the input datastream to this connection.

21SERIAL IN-PARALLEL OUT-1 Data is shifted in serially, but shifted out in parallel. In order to shift the data out in parallel, it is simply necessary tohave all the data bits available as outputs at the same time. E.g. 4-bit shift register

22SERIAL IN-PARALLEL OUT-1 E.g. 8-bit shift register

23SERIAL IN-PARALLEL OUT-2 How long will it take to shift an 8-bit number into a 8-bit shiftregister if the clock is set at 10 MHz? A minimum of eight clock periods will be required since thedata is entered serially. One clock period is 100 ns, so it willrequire 800 ns minimum.

24SERIAL IN-PARALLEL OUT-3 The waveforms shown below, show the typical response of a 54/74164. The serialdata is input at A (pin 1 ), while a gating control signal is applied at B (pin 2). Thefirst clear pulse occurs at time A and simply resets all flip-flops to 0.

25PARALLEL IN-SERIAL OUT-1 For a register with parallel data inputs, the bits are entered simultaneously into their respective stages on parallel lines rather than on a bit-by-bit basis on one line as withserial data inputs.Next slide illustrates a 4-bit parallel in/serial out shift register and a typical logicsymbol.Notice that there are four data-input lines, Do, D1 , D2 and D3 and a SHIFT/LOADinput, which allows four bits of data to load in parallel into the register.When SHIFT/LOAD is LOW, gates G1 through G4 are enabled, allowing each data bitto be applied to the D input of its respective flip-flop. When a clock pulse is applied,the flip-flops with D 1 will set and those with D 0 will reset. thereby storing allfour bits simultaneously.When SHIFT/LOAD is HIGH, gates G1 through G4 are disabled and gates G5 throughG 7 are enabled, allowing the data bits to shift right from one stage to the next.The OR gates allow either the normal shifting operation or the parallel data-entryoperation, depending on which AND gates are enabled by the level on theSHIFT/LOAD input.

26PARALLEL IN-SERIAL OUT-2 4-bit parallel in/serial out shift register.

27PARALLEL IN-SERIAL OUT-3 The 54/74166 is an 8-bitshift register.

28PARALLEL IN- PARALLEL OUT-1 The parallel in/parallel out register employs both methods.Immediately following the simultaneous entry of all data bits,the bits appear on the parallel outputs.

29PARALLEL IN- PARALLEL OUT-2 The 74174 is an example of a 6- bitparallel in-parallel out register.

30PARALLEL IN- PARALLEL OUT-3 The 74LS174 data sheet gives a setup time of 20 ns and a holdtime of 5 ns. What is the minimum required width of the datainput levels (D1 . D6) for the 74LS174?

31PARALLEL IN- PARALLEL OUT-4 The 5417495A describes it as a 4-bit parallel-access shift register. It also has serial data input andcan be used to shift data to the right (from QA toward QB) and in the opposite direction to the left.

32PARALLEL IN- PARALLEL OUT-4 The 5417495A describes it as a 4-bit parallel-access shift register. It also has serial data input andcan be used to shift data to the right (from QA toward QB) and in the opposite direction to the left.

33PARALLEL IN- PARALLEL OUT-5 Draw the waveforms you would expect ifthe 4-bit binary number l0l0 were shiftedinto a 5417495A in parallel. The mode control line must be high, Thedata. input line must be stable for more than10 ns prior to the clock NTs (setup time forthe data sheet information). A single clockNT will enter the data. If the clock isstopped after the transition time T, the levelson the input data lines may be changed,However, if the clock is not stopped, theinput data line levels must be maintained.

34UNIVERSAL SHIFT REGISTER-1 Basic types of shift register ,the following operations arepossible-serial in-serial out, serial in-parallel out, parallel inserial out, and parallel in-parallel out. Serial in or serial outagain can be made possible by shifting data in any of the twodirections, left shift (QA QB QC QD Data in) and rightshift (Data in QA QB QC QD). A universal shift registercan perform all the four operations and is also bidirectional innature.


36APPLICATIONS Of SHIFT REGISTERS-1 Shift register can be used to count number of pulses enteringinto a system as ring counter or switched-tail counter. As ringcounter it can generate various control signals in a sequentialmanner. Shift register can also generate a prescribed sequencerepetitively or detect a particular sequence from data input. Itcan also help in reduction of hardware by converting paralleldata feed to serial one. Serial adder is one such application discussed in this section.

37APPLICATIONS Of SHIFT REGISTERS-2 Ring Counter A ring counter is obtained from a shift registerby directly feeding back the true output of theoutput flip-flop to the data input terminal of theinput flip-flop. If D flip-flops are being used to construct theshift register, the ring counter, also called acirculating register, can be constructed byfeeding back the Q output of the output flip-flopback to the D input of the input 001510006010070010

38APPLICATIONS OF SHIFT REGISTERS-3 Flip-flop FF0 is initially set to the logic ‘1’ state and all other flip-flops arereset to the logic ‘0’ state. The counter output is therefore 1000. With the first clock pulse, this ‘1’ getsshifted to the second flip-flop output and the counter output becomes 0100. Similarly, with the second and third clock pulses, the counter output willbecome 0010 and 0001. With the fourth clock pulse, the counter output willagain become 1000. The count cycle repeats in the subsequent clock pulses.

39APPLICATIONS Of SHIFT REGISTERS-4 Waveforms of this type are frequently used in the control section of a digitalsystem. They are ideal for controlling events that must occur in a strict timesequence-that is, event A, then event B, then C, and so on. For instance, the logic diagram in figure shows how to generate RESET,READ, COMPLEMENT, and WRITE ( a fictitious set of control signals) as aset of control pulses that occur one after the other sequentially. There is, however, a problem with such ring counters. In order to produce thewaveforms shown in figure, the counter should have one, and only one, 1 in it.The chances of this occurring naturally when power is first applied are veryremote indeed. If the flip-flops should all happen to be in the reset state whenpower is first applied it will not work at all. One scheme how to do presetting when power is first applied.

40APPLICATIONS Of SHIFT REGISTERS-5 Switched-TailCounterorJohnsonCounter In Ring counter what happens if noninverting output of the first flip-flop is fedback to first flip flop of the shift register.If we instead feed inverting output back(or switch the tail) as shown in figure fora 4-bit shift register we get switched tailcounter, also known as twisted tailcounter or Johnson counter.

41APPLICATIONS Of SHIFT REGISTERS-6 From state table similar. Assume all the flip-flops are cleared in the beginning. Then all the flip-flop inputs have 0 except the first one, serial data in which iscomplement of the last flip-flop, i.e. 1.When clock trigger occurs flip-flop stores QRST as I 000. This makes 1100 at theinput of QRST when the next clock trigger comes and that gets transferred to outputat NT.Note that output Y Q'T' and state of the circuit repeats every eighth clock cycle.Thus this 4-bit shift register circuit can count 8 clock pulses or called modulo-8counter.Following above logic and preparing state table for any N-bit shift register we seeswitched-tail configuration can count up to 2N number of clock pulse and givesmodulo-2N counter. The output Y, derived similarly by AND operation of first andlast flip-flop inverting outputs gives a logic high at every 2N-th clock cycle.This two-input AND gate which decodes states repeating in the memory units togenerate output that signals counting of a given number of clock pulses is calleddecoding gate.

42APPLICATIONS Of SHIFT REGISTERS-7 Sequence Generator and Sequence Detector Sequence generator is useful in generating a sequence patternrepetitively. It may be the synchronizing hit pattern sent by a digital datatransmitter or it may be a control word directing repetitivecontrol task. Sequence detector checks binary data stream and generates asignal when a particular sequence is detected.

43APPLICATIONS Of SHIFT REGISTERS-8 Sequence Generator Figure gives the basic block diagram of a sequence generator where shiftregister is presented as pipe full of data and each flip-flop represents onecompartment of it. The leftmost flip-flop is connected to serial data in and rightmost providesserial data out. The clock is implied and data transfer takes place only when aclock trigger arrives. Note that the shift register is connected like a ring counter and with triggeringof clock the binary word stored in the clock comes out sequentially from serialout but does not get lost as it is fed back as serial in to fill the register all overagain. Sequence generated for binary word 1011 is shown in the figure and forany n-bit long sequence to be generated for this configuration we need to storethe sequence in an n-bit shift register.

44APPLICATIONS Of SHIFT REGISTERS-9 Sequence detector The circuit that can detect a 4-bit binary sequence is shown in figure. It has oneregister to store the binary word we want to detect from the data stream. Input datastream enters a shift register as serial data in and leaves as serial out. At every clocking instant, bit-wise comparisons of these two registers are donethrough Ex-NOR gate as shown in the figure. Two input Ex-NOR gives logic highwhen both inputs are low or both of them are high, i.e. when both are equal. Thefinal output is taken from a four input AND gate, which becomes 1 only when allits inputs are 1, i.e. all the bits are matched.

45APPLICATIONS Of SHIFT REGISTERS-10 Serial Adder For 8 bit full adder (FA) circuit need 8 FA units. There the addition is done inparallel. Using shift register we can convert this parallel addition to serial oneand reduce number of FA units to only one. The benefit of this technique ismore pronounced if the hardware unit that's needed to be used in parallel isvery costly.

46APPLICATIONS Of SHIFT REGISTERS-11 The LSBs of two numbers (A0 and B0) appearing at serial out of respective registers are added by FA during 1st clock cycle and generate sum (S0) and carry (C0). S0 isavailable at serial data input of register A and C0 at input of D flip-flop.At NT of clock shift registers shift its content to right by one unit. S0 becomes MSB ofA and C0 appears at D flip-flop output. Therefore in the second clock cycle FA is fed bysecond bit (A 1 and B 1) of two numbers and previous carry ( C0).In second clock cycle, S1 and C1 are generated and made available at serial data in of Aregister and input of D flip-flop respectively. At NT of clock S1 becomes MSB of A andSo occupies next position. A2 and B2 now appear at FA data input and carry input is C1.In 3rd clock cycle, S2 and C2 are generated and they get transferred similarly to registerand flip-flop. This process goes on and is stopped by inhibiting the clock after 8 clockcycles. At that time shift register A stores the sum bits, S7 in leftmost (MSB) positionand So in rightmost (LSB) position. The final carry is available at D flip-flop output.The limitation of this scheme is that the final addition result is delayed by eight clockcycles. In parallel adder the result is obtained almost instantaneously, after nanosecondorder propagation delay of combinatorial circuit. However, using a high frequency clockthe delay factor can be reduced considerably.

47REGISTER IMPLEMENTATION IN HDL-1The PIPO, When Clear is activated(active LOW) all 6 outputs of Q arereset.Shift right register , where T is thefinal output and Q, R, S are internaloutputs.module regpipo(D,clock,clear,Q);input Clock, clear;input [5:0] D;output [5:0] Q;reg [5:0] Q;[email protected] (negedge Clockor negedge Clear)if ( Clear) Q 6'b0;//Q stores 6 binary 0else Q D;endmodulemodule SRreg (D, Clock, T);input Clock, D;output T;reg T;reg Q,R,S;always @ (negedge Clock)beginQ D;R Q;S R;T S;endendmoduleSIPOmodule SR2(D,Clock,Q);input Clock, D;output [3:0] Q;reg [3 :O] Q;always @ (negedge clock)beginQ[0] D;Q[1] Q[0];Q[2] Q[1];Q[3] Q[2];endendmodule

48REGISTER IMPLEMENTATION IN HDL-2 Assignment operator within always block which unlike operator executes all associated statements concurrently. Assignment operator must start with begin

49REGISTER IMPLEMENTATION IN HDL-3 Write Verilog code for switched tail countermodule STC(Clock,Clear,Y); //Switched Tail Counterinput Clock, Clear;output Y;reg Q,R,S,T; //internal outputs of flip-flopsassign Y ( Q)&( T);[email protected] (negedge Clock)beginif ( Clear) Q 6'b0; //Q stores 6elsebeginQ T;//Tail is switched and connected to inputR Q;S R;T S;endendmodule

50PROBLEMMETHODSSOLVINGWITHMULTIPLE Design an 8-bit sequence generator that generates the sequence11000 l 00 repetitively using shift register.


52Introduction A counter driven by a clock can be used to count the number of clock cycles.Since the clock pulses occur at known intervals, the counter can be usedas an instrument for measuring time and therefore period or frequency.There are basically two different types of counters-synchronous andasynchronous.Serial, or asynchronous counter is defined as each flip-flop is triggered bythe previous flip-flop, and thus the counter has a cumulative settling time.An increase in speed of operation can be achieved by use of a parallel orsynchronous counter. Here, every flip-flop is triggered by the clock (insynchronism), and thus settling time is simply equal to the delay time of asingle flip-flop.Serial and parallel counters are used in combination to compromisebetween speed of operation and hardware count.

53ASYNCHRONOUS COUNTERS-1 The term asynchronous refers to events that do not have a fixed time relationship with eachother and, generally, do not occur at the same time. An asynchronous counter is one in which the flip-flops (FF) within the co

Introduction A register is simply a group of flip-flops that can be used to store a binary number. There must be one flip-flop for each bit in the binary number. A register is a digital circuit with two basic functions: data storage and data movement. E.g. a register used to store an 8-bit binary number must have eight flip-flops. Naturally the flip-flops must be connected such .