7 Series FPGAs PCB Design Guide (UG483) - Xilinx

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7 Series FPGAsPCB Design GuideUG483 (v1.14) May 21, 2019

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximumextent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALLWARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OFMERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whetherin contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arisingunder, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, orconsequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any actionbrought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may notreproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms andconditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP coresmay be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intendedto be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in suchcritical applications, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos.AUTOMOTIVE APPLICATIONS DISCLAIMERAUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENTOF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THEREIS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS,THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT ASAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNINGLIMITATIONS ON PRODUCT LIABILITY. Copyright 2011–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brandsincluded herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respectiveowners.Revision HistoryThe following table shows the revision history for this document.DateVersionRevision03/28/20111.0Initial Xilinx release.06/22/20111.1Updated Additional Support Resources.Updated Table 2-3 and added Table 2-4. Added 680 µF to Table 2-5. Updatedcapacitances in Bulk Capacitor Consolidation Rules.Updated Input Thresholds.08/16/20111.2Corrected FFG676 and FFG900 packages, and removed SBG324 package from Table 2-3.Added FFG1930 package to Table 2-4.In Figure 5-18 title, replaced “TDR” with “Return Loss.”12/15/20111.3Added Table 2-2. Updated Table 2-3 and Table 2-4. Updated Example, page 21 withKintex-7 device.03/19/20121.4Updated Table 2-2 and Table 2-4.10/02/20121.5Added FLG1926, HCG1155, HCG1931, and HCG1932 packages to Table 2-4. In Table 2-5,changed minimum ESR value for 100 µF capacitor from 10 mΩ to 2 mΩ.7 Series FPGAs PCB Design Guidewww.xilinx.comUG483 (v1.14) May 21, 2019

DateVersionRevision02/12/20131.6Updated first paragraph of Recommended PCB Capacitors per Device. Added FixedPackage Capacitors per Device. In Table 2-2, removed XC7A350T and added XC7A200T(SBG484). In Table 2-4, removed XC7V1500T and corrected packages for XC7VX1140Tfrom FFG to FLG. Added note about Pb-free packages to Table 2-2, Table 2-3, andTable 2-4. In Table 2-5, updated 680 µF, 47 µF, and 4.7 µF rows, and added second 330 µFrow. Added Table 2-6 to Table 2-9. Updated second paragraph of PCB Bulk Capacitors,page 23. Updated PCB Capacitor Placement and Mounting Techniques.06/13/20131.7Added RF676 and RF900 packages to Table 2-3. Added RF1157, RF1761, and RF1930packages to Table 2-4. In Table 2-5, updated 680 µF, 100 µF, 47 µF, and 4.7 µF rows.Added RF676 and RF900 packages to Table 2-6. Added RF1157, RF1761, and RF1930packages to Table 2-8. Added capacitor V to PCB Bulk Capacitors, page 23 and PCB BulkCapacitors, page 24. In 0402 Ceramic Capacitors, replaced 0805 ceramic capacitor with0402. Updated Figure 2-1. In Figure 2-6, replaced 0805 capacitor with 0402.09/13/20131.8Added Artix-7 devices XC7A35T, XC7A50T, and XC7A75T to and updated Table 2-2.Removed this note: All packages listed are Pb-free. Some packages are available in Pb optionfrom Table 2-3, Table 2-6, and Table 2-8. Removed Note 4 from Table 2-4.05/13/20141.9In Recommended PCB Capacitors per Device, added reference to XMP277, 7 SeriesSchematic Review Recommendations. In Table 2-2, corrected VCCO Bank 0 capacitance from4.7 µF to 47 µF; added 100 µF to VCCO all other Banks column; added CPG236, CSG325,RB484, RS484, and RB676 packages; added XA7A35T, XA7A50T, XA7A75T, XA7A100T,XQ7A50T, XQ7A100T, and XQ7A200T devices; and updated Note 3. Added this note:“Decoupling capacitors cover down to approximately 100 KHz” to Table 2-2, Table 2-3,and Table 2-4. Added 47 µF to VCCO all other Banks column in Table 2-3 and Table 2-4.In Table 2-4, added FLG1155 and FLG1931 packages for XC7VH580T, removedHCG1932 package for XC7VH580T, removed HCG1931 package for XC7VH870T, andadded FLG1932 package for XC7VH870T. Updated Table 2-5, including the addition of0.47 µF. In Table 2-8, added FLG1155 and FLG1931 packages for XC7VH580T, removedHCG1931 package for XC7VH870T, removed HCG1932 package for XC7VH580T, andadded FLG1932 package for XC7VH870T. Updated list of bulk capacitors in PCB BulkCapacitors, page 23 and added note. Replaced 0402 with 0805 package in PCB HighFrequency Capacitors. Removed Example section from Bulk Capacitor ConsolidationRules. Updated list of bulk capacitors in PCB Bulk Capacitors, page 24. In 0805 and 0603Ceramic Capacitors, replaced 0402 with 0805 and 0603 capacitors. Removed 0402 fromFigure 2-1. Updated first paragraph of Noise Limits. Added VCCAUX IO to PowerSupply Consolidation. Updated last paragraph of Unconnected VCCO Pins. Updatedparagraph after Figure 2-9.11/12/20141.10Removed “pin planning” from document title. Added reference to 7 Series FPGAsPackaging and Pinout Product Specification User Guide in Lands. Added XC7A15T andXA7A15T devices to Table 2-2. Added note about 47 µF capacitor being required forVCCO banks to Table 2-3 and Table 2-4 and updated the same to note 3 in Table 2-2.Removed VRIPPLE from Noise Limits.04/07/20161.11Added FBV484, FBV676, and FFV1156 packages to Table 2-2 and deleted Note 4 (Allpackages listed are Pb-free. Some packages are available in Pb option). Added FBV484, FBV676,FFV676, FBV900, FFV900, FFV901, and FFV1156 packages to Table 2-3. Added FFV1157,FFV1158, RF1158, FFG1761, and FFV1927 packages to Table 2-4. Added FBV484,FBV676, FFV676, FBV900, FFV900, FFV901, and FFV1156 packages to Table 2-6. AddedFFV1157, FFV1158, RF1158, FFV1761, and FFV1927 packages and device XQ7VX690T toTable 2-6. Added FFV1157, FFV1158, RF1158, FFV1761, and FFV1927 packages toTable 2-8.UG483 (v1.14) May 21, 2019www.xilinx.com7 Series FPGAs PCB Design Guide

DateVersionRevision01/10/20171.12Updated introductory paragraph in About This Guide. Changed “100 MHz” to“10 MHz” in third paragraph, updated fourth paragraph, and added “GTP” and UG482reference in last paragraph under Recommended PCB Capacitors per Device. AddedTable 2-1 for Spartan-7 devices. Added XC7A12T and XC7A25T devices to Table 2-2.08/18/20171.13In Table 2-1: Added FTGB196 package for XC7S6, XC7S15, XC7S25, and XC7S50 devices.Added FGGA676 package for XC7S75 device.Removed VCCINT columns at 680 µF and 47 µF.Removed VCCO bank 0 column.Removed note 5.In Table 2-2, replaced CPG236 with CPG238 package for XC7A12T and XC7A25Tdevices, and added capacitance values for CSG325 package in XC7A12T and XC7A25Tdevices. Removed HCG1155, HCG1931, and HCG1931 packages from Table 2-4 andTable 2-8 per the customer notice XCN14005, Product Discontinuation Notice ForVirtex-7 HT FPGA HCG Packages. In Table 2-11, replaced Agilent and Sigrity vendorswith Cadence.05/21/20191.14Added XA7K160T to Table 2-3 and Table 2-6.7 Series FPGAs PCB Design Guidewww.xilinx.comUG483 (v1.14) May 21, 2019

Table of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Chapter 1: PCB Technology BasicsPCB Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Pads and Antipads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Lands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Return Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Chapter 2: Power Distribution SystemPCB Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Recommended PCB Capacitors per Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Fixed Package Capacitors per Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Capacitor Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Bulk Capacitor Consolidation Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PCB Capacitor Placement and Mounting Techniques . . . . . . . . . . . . . . . . . . . . . . . . . .1314192424Basic PDS Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Noise Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Role of Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Capacitor Parasitic Inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PCB Current Path Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Plane Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Capacitor Effective Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Capacitor Anti-Resonance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Capacitor Placement Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VREF Stabilization Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Power Supply Consolidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Unconnected VCCO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2527272930333435363636Simulation Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36PDS Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Noise Magnitude Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Noise Spectrum Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Optimum Decoupling Network Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Possibility 1: Excessive Noise from Other Devices on the PCB . . . . . . . . . . . . . . . . . . 42Possibility 2: Parasitic Inductance of Planes, Vias, or Connecting Traces . . . . . . . . . . 427 Series FPGAs PCB Design GuideUG483 (v1.14) May 21, 2019www.xilinx.comSend Feedback5

Possibility 3: I/O Signals in PCB are Stronger Than Necessary . . . . . . . . . . . . . . . . . . 43Possibility 4: I/O Signal Return Current Traveling in Sub-Optimal Paths . . . . . . . . . 43Chapter 3: SelectIO SignalingInterface Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Single-Ended versus Differential Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45SDR versus DDR Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Single-Ended Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Modes and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Input Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Topographies and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Chapter 4: PCB Materials and TracesHow Fast is Fast? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Dielectric Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Relative Permittivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Loss Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Skin Effect and Resistive Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Choosing the Substrate Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57585858Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Trace Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Trace Characteristic Impedance Design for High-Speed Transceivers . . . . . . . . . . . .Trace Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Plane Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Return Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Simulating Lossy Transmission Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .595961616162Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Skew Between Conductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Chapter 5: Design of Transitions for High-Speed SignalsExcess Capacitance and Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Time Domain Reflectometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SMT Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Differential Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P/N Crossover Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SMA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Backplane Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Microstrip/Stripline Bends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Send Feedbackwww.xilinx.com6363656570737373737 Series FPGAs PCB Design GuideUG483 (v1.14) May 21, 2019

PrefaceAbout This GuideXilinx 7 series FPGAs include four FPGA families that are all designed for lowest powerto enable a common design to scale across families for optimal power, performance, andcost. The Spartan -7 family is the lowest density with the lowest cost entry point into the7 series portfolio. The Artix -7 family is optimized for highest performance-per-watt andbandwidth-per-watt for cost-sensitive, high volume applications. The Kintex -7 family isan innovative class of FPGAs optimized for the best price-performance. The Virtex -7family is optimized for highest system performance and capacity.This guide provides information on PCB design for 7 series FPGAs, with a focus onstrategies for making design decisions at the PCB and interface level. This 7 series FPGAsPCB design user guide is part of an overall set of documentation on the 7 series FPGAs,which is available on the Xilinx website at www.xilinx.com/documentation.Guide ContentsThis guide contains the following chapters: Chapter 1, PCB Technology Basics, discusses the basics of current PCB technologyfocusing on physical structures and common assumptions. Chapter 2, Power Distribution System, covers the power distribution system for7 series FPGAs, including all details of decoupling capacitor selection, use of voltageregulators and PCB geometries, simulation and measurement. Chapter 3, SelectIO Signaling, contains information on the choice of SelectIO standards, I/O topographies, and termination strategies as well as information onsimulation and measurement techniques. Chapter 4, PCB Materials and Traces, provides some guidelines on managing signalattenuation to obtain optimal performance for high-frequency applications. Chapter 5, Design of Transitions for High-Speed Signals, addresses the interface ateither end of a transmission line. The provided analyses and examples can greatlyaccelerate the specific design.Additional Support ResourcesTo find additional documentation, see the Xilinx support website at:http://www.xilinx.com/support.7 Series FPGAs PCB Design GuideUG483 (v1.14) May 21, 2019www.xilinx.comSend Feedback7

Preface:8About This GuideSend Feedbackwww.xilinx.com7 Series FPGAs PCB Design GuideUG483 (v1.14) May 21, 2019

Chapter 1PCB Technology BasicsPrinted circuit boards (PCBs) are electrical systems, with electrical properties ascomplicated as the discrete components and devices mounted to them. The PCB designerhas complete control over many aspects of the PCB; however, current technology placesconstraints and limits on the geometries and resulting electrical properties. The followinginformation is provided as a guide to the freedoms, limitations, and techniques for PCBdesigns using FPGAs.This chapter contains the following sections: PCB Structures Transmission Lines Return CurrentsPCB StructuresPCB technology has not changed significantly in the last few decades. An insulatorsubstrate material (usually FR4, an epoxy/glass composite) with copper plating on bothsides has portions of copper etched away to form conductive paths. Layers of plated andetched substrates are glued together in a stack with additional insulator substratesbetween the etched substrates. Holes are drilled through the stack. Conductive plating isapplied to these holes, selectively forming conductive connections between the etchedcopper of different layers.While there are advancements in PCB technology, such as material properties, the numberof stacked layers used, geometries, and drilling techniques (allowing holes that penetrateonly a portion of the stackup), the basic structures of PCBs have not changed. Thestructures formed through the PCB technology are abstracted to a set of physical/electricalstructures: traces, planes (or planelets), vias, and pads.TracesA trace is a physical strip of metal (usually copper) making an electrical connectionbetween two or more points on an X-Y coordinate of a PCB. The trace carries signalsbetween these points.PlanesA plane is an uninterrupted area of metal covering the entire PCB layer. A planelet, avariation of a plane, is an uninterrupted area of metal covering only a portion of a PCBlayer. Typically, a number of planelets exist in one PCB layer. Planes and planeletsdistribute power to a number of points on a PCB. They are very important in the7 Series FPGAs PCB Design GuideUG483 (v1.14) May 21, 2019www.xilinx.comSend Feedback9

Chapter 1:PCB Technology Basicstransmission of signals along traces because they are the return current transmissionmedium.ViasA via is a piece of metal making an electrical connection between two or more points in theZ space of a PCB. Vias carry signals or power between layers of a PCB. In current platedthrough-hole (PTH) technology, a via is formed by plating the inner surface of a holedrilled through the PCB. In current microvia technology (also known as High DensityInterconnect or HDI), a via is formed with a laser by ablating the substrate material anddeforming the conductive plating. These microvias cannot penetrate more than one or twolayers, however, they can be stacked or stair-stepped to form vias traversing the full boardthickness.Pads and AntipadsBecause PTH vias are conductive over the whole length of the via, a method is needed toselectively make electrical connections to traces, planes, and planelets of the various layersof a PCB. This is the function of pads and antipads.Pads are small areas of copper in prescribed shapes. Antipads are small areas in prescribedshapes where copper is removed. Pads are used both with vias and as exposed outer-layercopper for mounting of surface-mount components. Antipads are used mainly with vias.For traces, pads are used to make the electrical connection between the via and the trace orplane shape on a given layer. For a via to make a solid connection to a trace on a PCB layer,a pad must be present for mechanical stability. The size of the pad must meet drilltolerance/registration restrictions.Antipads are used in planes. Because plane and planelet copper is otherwiseuninterrupted, any via traveling through the copper makes an electrical connection to it.Where vias are not intended to make an electrical connection to the planes or planeletspassed through, an antipad removes copper in the area of the layer where the viapenetrates.LandsFor the purposes of soldering surface mount components, pads on outer layers aretypically referred to as lands or solder lands. Making electrical connections to these landsusually requires vias. Due to manufacturing constraints of PTH technology, it is rarelypossible to place a via inside the area of the land. Instead, this technology uses a shortsection of trace connecting to a surface pad. The minimum length of the connecting trace isdetermined by minimum dimension specifications from the PCB manufacturer. Microviatechnology is not constrained, and vias can be placed directly in the area of a solder land.For further information regarding PCB lands and BGA packages, refer to the“Recommended PCB Design Rules for BGA Packages” appendix of 7 Series FPGAsPackaging and Pinout Product Specification User Guide (UG475).DimensionsThe major factors defining the dimensions of the PCB are PCB manufacturing limits, FPGApackage geometries, and system compliance. Other factors such as Design ForManufacturing (DFM) and reliability impose further limits, but because these areapplication specific, they are not documented in this user guide.10Send Feedbackwww.xilinx.com7 Series FPGAs PCB Design GuideUG483 (v1.14) May 21, 2019

Transmission LinesThe dimensions of the FPGA package, in combination with PCB manufacturing limits,define most of the geometric aspects of the PCB structures described in this section (PCBStructures), both directly and indirectly. This significantly constrains the PCB designer. Thepackage ball pitch (1.0 mm for FF packages) defines the land pad layout. The minimumsurface feature sizes of current PCB technology define the via arrangement in the areaunder the device. Minimum via diameters and keep-out areas around those vias are definedby the PCB manufacturer. These diameters limit the amount of space available in-betweenvias for routing of signals in and out of the via array underneath the device. Thesediameters define the maximum trace width in these breakout traces. PCB manufacturinglimits constrain the minimum trace width and minimum spacing.The total number of PCB layers necessary to accommodate an FPGA is defined by thenumber of signal layers and the number of plane layers. The number of signal layers is defined by the number of I/O signal traces routed inand out of an FPGA package (usually following the total User I/O count of thepackage). The number of plane layers is defined by the number of power and ground planelayers necessary to bring power to the FPGA and to provide references and isolationfor signal layers.Most PCBs for large FPGAs range from 12 to 22 layers.System compliance often defines the total thickness of the board. Along with the numberof board layers, this defines the maximum layer thickness, and therefore, the spacing in theZ direction of signal and plane layers to other signal and plane layers. Z-direction spacingof signal trace layers to other signal trace layers affects crosstalk. Z-direction spacing ofsignal trace layers to reference plane layers affects signal trace impedance. Z-directionspacing of plane layers to other plane layers affects power system parasitic inductance.Z-direction spacing of signal trace layers to reference plane layers (defined by total boardthickness and number of board layers) is a defining factor in trace impedance.Trace width(defined by FPGA package ball pitch and PCB via manufacturing constraints) is anotherfactor in trace impedance. A designer often has little control over trace impedance in areaof the via array beneath the FPGA. When traces escape the via array, their width canchange to the width of the target impedance (usually 50Ω single-ended).Decoupling capacitor placement and discrete termination resistor placement are otherareas of trade-off optimization. DFM constraints often define a keep-out area around theperimeter of the FPGA (device footprint) where no discrete components can be placed. Thepurpose of the keep-out area is to allow room for assembly and rework where necessary.For this reason, the area just outside the keep-out area is one where components competefor placement. It is up to the PCB designer to determine the high priority components.Decoupling capacitor placement constraints are described in Chapter 2, PowerDistribution System. Termination resistor placement constraints must be determinedthrough signal integrity simulation, using IBIS or SPICE.Transmission LinesThe combination of a signal trace and a reference plane forms a transmission line. All I/Osignals in a PCB system travel through transmission lines.For single-ended I/O interfaces, both the signal trace and the reference plane are necessaryto transmit a signal from one place to another on the PCB. For differential I/O interfaces,the transmission line is formed by the combination of two traces and a reference plane.7 Series FPGAs PCB Design GuideUG483 (v1.14) May 21, 2019www.xilinx.comSend Feedback11

Chapter 1:PCB Technology BasicsWhile the presence of a reference plane is not strictly necessary in the case of differentialsignals, it is necessary for practical implementation of differential traces in PCBs.Good signal integrity in a PCB system is dependent on having transmission lines withco

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