7 Series FPGAs GTP Transceivers - Xilinx

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7 Series FPGAsGTP TransceiversUser GuideUG482 (v1.9) December 19, 2016

DISCLAIMERThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximumextent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIESAND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, includingnegligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with,the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if suchdamage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correctany errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce,modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditionsof Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may besubject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to befail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in suchcritical applications, please refer to Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos.AUTOMOTIVE APPLICATIONS DISCLAIMERAUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGSOR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT ORREDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL,PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETYPURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLYTO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. Copyright 2012–2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brandsincluded herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respectiveowners.Revision HistoryThe following table shows the revision history for this document.DateVersionRevision01/03/20121.0Initial Xilinx release.02/21/20121.1Changed “N” factor to “N1” and “N2”factors in Figure 2-10, Equation 2-1, and Table 2-7.Revised Figure A-4, Figure A-6, Table B-1, Table D-1, and Table D-2.01/01/20121.1.109/06/20121.2Made typographical edits.Updated the second, third, and fourth paragraphs under Overview and Features in Chapter 1.Updated description of PLL0 FBDIV/PLL1 FBDIV and added PLL0 FBDIV 45/PLL0 FBDIV 45 attributes to Table 2-9. Added Reset and Initialization and Power Down inChapter 2. Updated Note 1 relevant to Figure 3-2 through Figure 3-5. Updated descriptions ofTXSTARTSEQ and GEARBOX MODE attributes in Table 3-9. Updated controller port clockdomains and descriptions in Table 3-26. Updated TXPI SYNFREQ PPM[2:0] andTXPI GREY SEL attribute descriptions in Table 3-27. Updated first introductory paragraphunder TX Gearbox Operating Modes in Chapter 3. Deleted Internal Sequence Counter OperatingMode section in Chapter 3, Transmitter. Added USE PCS CLK PHASE SEL andES CLK PHASE SE attributes to Table 4-20. Added second and third paragraphs underAlignment Status Signals in Chapter 4. Added last sentence to description ofRXBYTEISALIGNED port in Table 4-25. Added COMMA ALIGN LATENCY attribute toTable 4-26. Updated description of GEARBOX MODE attribute in Table 4-42. AddedChapter 5, Board Design Guidelines. Updated all package drawings in Appendix A, PlacementInformation by Package. Updated Table B-1.7 Series FPGAs GTP Transceivers User Guidewww.xilinx.comUG482 (v1.9) December 19, 2016

DateVersionRevision10/23/20121.3Added Artix-7 device in Functional Description, page 25, Single External Reference Clock UseModel, page 32, and Multiple External Reference Clock Use Model, page 33. DeletedXC7A350T in Figure 3-4 and Figure 3-5 footnotes. Deleted PCIe Protocol in Table 4-3. DeletedXC7A350T devices in Table 5-2 and Figure 5-3. Added additional ceramic filter capacitor toMGTAVCC G[N} and MGTAVTT G[N] pins in Table 5-14. Deleted XC7A350T in Figure A-9,Figure A-10, Figure A-11, Figure A-12, Figure A-13, and Figure A-14. Deleted XC7A350T inTable B-1.02/21/20131.4Replaced references to GTX transceiver with references to GTP transceiver throughoutdocument.Chapter 2: Updated Figure 2-2, Figure 2-12, Figure 2-13, Figure 2-14, Figure 2-15, Figure 2-16,and Figure 2-17. Updated Table 2-6, rows one and two, and Table 2-8, rows one and four. RevisedReset and Initialization, last paragraph on page 40. Updated Table 2-14, rows five and six. AddedTable 2-17, and sections After Power-up and Configuration, page 47, through TX Parallel ClockSource Reset, page 47. Updated Table 2-18, rows two, three, four, seven, twelve, thirteen, fifteen,and seventeen. Updated Figure 2-19 and added notes relevant to the figure. Updated Figure 2-20and added notes relevant to the figure. Added GTP Transceiver RX PMA Reset, page 56,including Figure 2-21 and notes relevant to the figure. Revised GTP Transceiver RX ComponentResets, page 56 by adding Table 2-22 and sections After Power-up and Configuration, page 47through After Comma Realignment, page 61. Revised Loopback Functional description onpage 65. Updated Table 2-28, row two. Updated Table 2-29, rows three and seven and Table 2-30,rows three and seven. Added Digital Monitor, page 70 through page 75.Chapter 3: Revised section TX Buffer Bypass, page 95 through page 106. Updated Figure 3-20.Updated Table 3-24, rows three and five, and Table 3-24, row three.Chapter 4: Updated Table 4-3, Table 4-4, Table 4-5, Table 4-6, rows five and six, and Table 4-7,row twelve. Added Use Mode, page 132 through Figure 4-14, page 138. Added section UseModes, page 144 through Table 4-15. Updated Figure 4-18. Updated Table 4-17, rows three andfive. Added section Using RXRATE, page 149 through page 150. Revised section RX BufferBypass, page 173 through page 186. Updated Table 4-33 and Table 4-33, rows five and ten.Chapter 5: Updated Table 5-2, rows one and two, and Table 5-11, rows three and four.Appendix A: Updated Figure A-4 through Figure A-14.Appendix B: Updated Table B-1.04/15/20131.5Added last two rows in Table 2-22. Added three sentences to Loopback Functional Description,page 25. Changed “DEN” to “DRPEN” in Table 2-29 and Table 2-30. Added a note toFigure 2-23 and Figure 2-24. Revised TX Buffer Bypass Functional Description, page 93 andTable 3-15. Revised TX Buffer Bypass Use Modes, page 98, deleted Figure 3-12, TX BufferBypass, Single lane Auto mode Port Connection, and replaced Figure 3-12 and notes relevant toit. Revised Using TX Buffer Bypass in Multi-Lane Mode, page 100 (and removed “Manual” fromsection title and text). Deleted section titled “Using TX Buffer Bypass in Multi Lane Auto Mode.”Added last two rows to Table 4-2. Changed “INCP” to “IPCM” in Table 4-3, Table 4-4, andTable 4-5. Changed RXCDR CFG attribute type from 72- to 83-bit hex in Table 4-12.08/28/20131.6Added devices XC7A35T-CSG325 (Preliminary), XC7A35T-FGG484 (Preliminary),XC7A50T-CSG325 (Preliminary), XC7A50T-FGG484 (Preliminary), XC7A75T-FGG484, andXC7A75T-FGG676.UG482 (v1.9) December 19, 2016www.xilinx.com7 Series FPGAs GTP Transceivers User Guide

DateVersionRevision04/03/20141.7Added devices XC7A35T-CPG236, XC7A50T-CPG236, and XC7Z015-CLG485. ChangedSIM VERSION type from “Real” to “String” in Table 1-3. Changed RX rate change from “RXPCS” to “Entire RX” in Table 2-22. Expanded RX Rate Change, page 60. Expanded descriptionsfor DRPEN in Table 2-29 and Table 2-30. Modified the descriptions for RXOSCALRESETthrough RXOSINTDONE in Table 4-11. Changed direction of RXCHARISK[3:0] from “In” to“Out” in Table 4-27. Updated Table 5-2 and Figure 5-3 for new devices/packages. AddedTable 5-3, Table 5-8, Table 5-9, and Table 5-10, for new devices/packages. Expanded SelectIOUsage Guidelines, page 235. Added CPG236, CSG325, and CLG485 package placementdiagrams (Figure A-1, Figure A-2, and Figure A-3). Updated Figure A-4 for new devices.Updated Table B-1 and added Table B-2 for new devices.11/19/20141.8Added device XC7A15T (-CSG325, -CPG236, and -FGG484 packages). Enhanced descriptionsfor port O and ODIV2 in Table 2-1. Added ports BGBYPASSB, BGMONITORENB, BGPDB,BGRCALOVRD, and RCALENB to Table 2-8. Added last two rows to Table 2-17. Added secondparagraph under PLL Power Down, page 63. Updated digital monitor Functional Description,page 70 and added ports DMONITORCLK and DMONFIFORESET to Table 2-31.12/19/20161.9Added Spartan -7 device family: Updated Preface, Table 5-2, Table 5-3, Table B-1, Table B-2,Figure 5-3, Figure A-1, and Figure A-2.7 Series FPGAs GTP Transceivers User Guidewww.xilinx.comUG482 (v1.9) December 19, 2016

Table of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Additional References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Chapter 1: Transceiver and Tool OverviewOverview and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Series FPGAs Transceivers Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11161620Chapter 2: Shared FeaturesReference Clock Input Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Reference Clock Selection and Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Dynamic Reconfiguration Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Digital Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2325343861646770Chapter 3: TransmitterTX Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75FPGA TX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76TX 8B/10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83TX Gearbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86TX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93TX Buffer Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95TX Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103TX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106TX Fabric Clock Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107TX Phase Interpolator PPM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111TX Configurable Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114TX Receiver Detect Support for PCI Express Designs . . . . . . . . . . . . . . . . . . . . . . . . . . 121TX Out-of-Band Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016www.xilinx.comSend Feedback5

Chapter 4: ReceiverRX Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Out-of-Band Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Fabric Clock Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Margin Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Pattern Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Byte and Word Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX 8B/10B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Buffer Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RX Gearbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .FPGA RX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Chapter 5: Board Design GuidelinesOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Pin Description and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Power Supply and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SelectIO Usage Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PCB Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217217224228235235Appendix A: Placement Information by PackageCPG236 Package Placement Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CSG325 Package Placement Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CLG485 Package Placement Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .FGG484 Package Placement Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .FGG676 Package Placement Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .FBG484 Package Placement Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SBG484 Package Placement Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .FBG676 Package Placement Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .FFG1156 Package Placement Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Send Feedbackwww.xilinx.com2382392402412422442452462487 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016

Appendix B: Placement Information by DeviceAppendix C: 8B/10B Valid CharactersAppendix D: DRP Address Map of the GTP Transceiver7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016www.xilinx.comSend Feedback7

8Send Feedbackwww.xilinx.com7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016

PrefaceAbout This GuideXilinx 7 series FPGAs include four FPGA families that are all designed for lowest power to enablea common design to scale across families for optimal power, performance, and cost. The Spartan -7family is the lowest density with the lowest cost entry point into the 7 series portfolio. The Artix -7family is optimized for highest performance-per-watt and bandwidth-per-watt for cost-sensitive,high-volume applications. The Kintex -7 family is an innovative class of FPGAs optimized for thebest price-performance. The Virtex -7 family is optimized for highest system performance andcapacity. This guide serves as a technical reference describing the 7 series FPGAs GTP transceivers.The 7 series FPGAs GTP transceivers user guide, part of an overall set of documentation on the7 series FPGAs, is available on the Xilinx website at xilinx.com/documentation.In this document: 7 series FPGAs GTP transceiver channel is abbreviated as GTP transceiver. GTPE2 CHANNEL is the name of the instantiation primitive that instantiates one GTPtransceiver channel. GTPE2 COMMON is the name of the primitive that instantiates two ring oscillator PLLs(PLL0 and PLL1). A Quad or Q is a cluster or set of four GTP transceiver channels, one GTPE2 COMMONprimitive, two differential reference clock pin pairs, and analog supply pins.Guide ContentsThis manual contains: Chapter 1, Transceiver and Tool Overview Chapter 2, Shared Features Chapter 3, Transmitter Chapter 4, Receiver Chapter 5, Board Design Guidelines Appendix A, Placement Information by Package Appendix B, Placement Information by Device Appendix C, 8B/10B Valid Characters Appendix D, DRP Address Map of the GTP Transceiver7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016www.xilinx.comSend Feedback9

Preface:About This GuideAdditional ResourcesTo find additional documentation, see the Xilinx website ex.htm.To search the Answer Database of silicon, software, and IP questions and answers, or to create atechnical support WebCase, see the Xilinx website at:http://www.xilinx.com/support.Additional ReferencesThese documents provide additional information useful to this document:1.High-Speed Serial I/O Made books/serialio.pdf10Send Feedbackwww.xilinx.com7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016

Chapter 1Transceiver and Tool OverviewOverview and FeaturesThe 7 series FPGAs GTP transceiver is a power-efficient transceiver, supporting line rates between500 Mb/s and 6.6 Gb/s. The GTP transceiver is highly configurable and tightly integrated with theprogrammable logic resources of the FPGA. Table 1-1 summarizes the features by functional groupthat support a wide variety of applications.Table 1-1: 7 Series FPGAs Transceiver FeaturesGroupPCSFeature2-byte internal datapathGTPGTXGTHxxxxx4-byte internal datapathPMA8B/10B encoding and decodingxxx64B/66B and 64B/67B supportxxxComma detection and byte and word alignmentxxxPRBS generator and checkerxxxFIFO for clock correction and channel bondingxxxProgrammable FPGA logic interfacexxxOne shared LC tank PLL per QuadxxOne ring oscillator PLL per channelxxxxxxTwo shared ring oscillator PLLs per QuadxFlexible reference clocking optionsxDecision feedback equalization (DFE)Power-efficient adaptive linear equalizer mode called the low-power mode (LPM)xxxTX Pre-emphasisxxxBeacon signaling for PCI Express designsxxxOut-of-band (OOB) signaling including COM signal support for Serial ATA (SATA)designsxxxRX Margin Analysisxxx7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016www.xilinx.comSend Feedback11

Chapter 1:Transceiver and Tool OverviewThe GTP transceiver offers a data rate range and features that allow physical layer support forvarious protocols including: PCI Express, Revision 1.1/2.0 Interlaken 10 Gb Attachment Unit Interface (XAUI), Reduced Pin eXtended Attachment Unit Interface(RXAUI) Common Packet Radio Interface (CPRI )/Open Base Station Architecture Initiative (OBSAI) OC-48 OTU-1 Serial RapidIO (SRIO) Serial Advanced Technology Attachment (SATA)/Serial Attached SCSI (SAS) Serial Digital Interface (SDI)The CORE Generator tool includes a wizard to automatically generate predefined settings toconfigure GTP transceivers to support configurations for different protocols. The wizard can also beused to create custom configurations. For a complete list of protocols and electrical specificationsenabled through predefined settings, please refer to PG168, 7 Series FPGAs Transceivers WizardLogiCORE IP Product Guide.In comparison to prior generation transceivers in Spartan -6 FPGAs, the GTP transceiver in the 7series FPGAs has the following new or enhanced features: 2-byte internal datapath Two ring oscillator PLLs per Quad Power-efficient, adaptive continuous time linear equalizer (CTLE) RX margin analysis feature to provide non-destructive, 2-D post-equalization eye scan.The first-time user is recommended to read High-Speed Serial I/O Made Simple [Ref 1], whichdiscusses high-speed serial transceiver technology and its applications.Figure 1-1, page 13 shows the GTP transceiver placement in an example Artix -7 device(XC7A100T). This device has 8 GTP transceivers.12Send Feedbackwww.xilinx.com7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016

Overview and FeaturesX-Ref Target - Figure 1-1Artix-7 FPGA (XC7A100T)GTP QuadGTPE2 CHANNEL X0Y7IntegratedBlock for Y1GTPE2 CHANNEL X0Y6GTPE2 CHANNEL X0Y5GTPE2 CHANNEL X0Y4CMTColumnConfigurationI/OColumnGTP QuadGTPE2 CHANNEL X0Y3GTPE2COMMONX0Y0GTPE2 CHANNEL X0Y2GTPE2 CHANNEL X0Y1GTPE2 CHANNEL X0Y0UG482 C1 01 110811Figure 1-1:GTP Transceiver Inside Artix-7 XC7A100T FPGAAdditional information on the functional blocks of 7 series FPGAs is available at:UG470, 7 Series FPGAs Configuration User Guide provides more information on theconfiguration.UG471, 7 Series FPGAs SelectIO Resources User Guide provides more information on the I/Oblocks.UG472, 7 Series FPGAs Clocking Resources User Guide provides more information on themixed mode clock manager (MMCM).Figure 1-2 illustrates the clustering of four GTPE2 CHANNEL primitives and oneGTPE2 COMMON primitive to form a Quad.7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016www.xilinx.comSend Feedback13

Chapter 1:Transceiver and Tool OverviewX-Ref Target - Figure 1-2GTPE2 CHANNELRXTXGTPE2 CHANNELRXGTPE2 CHANNELTXRXPLL0GTPE2 CHANNELTXRXTXPLL1GTPE2 COMMONREFCLK DistributionIBUFDS GTE2IBUFDS GTE2UG482 c1 02 110811Figure 1-2:GTP Transceiver Quad ConfigurationFour GTPE2 channels clustered together with one GTPE2 COMMON primitive are called a Quador Q.The GTPE2 COMMON primitive contains two ring oscillator PLLs (PLL0 and PLL1).GTPE2 COMMON must always be instantiated.Each GTPE2 CHANNEL primitive consists of a transmitter and a receiver.14Send Feedbackwww.xilinx.com7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016

Overview and FeaturesFigure 1-3 illustrates the topology of a GTPE2 CHANNEL primitive.X-Ref Target - Figure 1-3TXTXOOBDriver andPCIeTX FOPolarityTX PIPEControl8B/10BEncoderTX PhaseInterpolatorControllerTX PhaseInterpolatorTX-PMAClock From PLL0 or PLL1Clock From PLL0 or PLL1TX-PCSTo RX ParallelData (Near-EndPCS Loopback)From RX Parallel Data(Far-End PMA Loopback)RX ClockDividersCommaDetectAndAlignFrom RX Parallel Data(Far-End PCS Loopback)RX PIPE ControlRX EQRX Status ControlRX ferPolarity8B/10BDecoderSIPOUG482 c1 03 110811Figure 1-3:GTPE2 CHANNEL Primitive TopologyRefer to Figure 2-9, page 35 for the description of the channel clocking architecture, which providesclocks to the RX and TX clock dividers.7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016www.xilinx.comSend Feedback15

Chapter 1:Transceiver and Tool Overview7 Series FPGAs Transceivers WizardThe 7 Series FPGAs Transceivers Wizard (hereinafter called the Wizard) is the preferred tool togenerate a wrapper to instantiate GTP transceiver primitives called GTPE2 COMMON andGTPE2 CHANNEL. The Wizard is located in the CORE Generator tool. The user is recommendedto download the most up-to-date IP update before using the Wizard. Details on how to use thisWizard can be found in PG168, 7 Series FPGAs Transceivers Wizard LogiCORE IP Product Guide.Follow these steps to launch the Wizard:1.Start the CORE Generator tool.2.Locate the 7 Series FPGAs Transceivers Wizard in the taxonomy tree under:/FPGA Features & Design/IO InterfacesSee Figure 1-4.X-Ref Target - Figure 1-4UG482 c1 04 110911Figure 1-4:3.7 Series FPGAs Transceivers WizardDouble-click 7 Series FPGAs Transceivers Wizard to launch the Wizard.SimulationFunctional DescriptionSimulations using the GTPE2 CHANNEL and GTPE2 COMMON primitives have specificprerequisites that the simulation environment and the test bench must fulfill. For instructions on howto set up the simulation environment for supported simulators depending on the used hardwaredescription language (HDL), see the latest version of UG626, Synthesis and Simulation DesignGuide.The prerequisites for simulating a design with the GTPE2 CHANNEL and GTPE2 COMMONprimitives are: 16A simulator with support for SecureIP models.Send Feedbackwww.xilinx.com7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016

SimulationSecureIP models are encrypted versions of the Verilog HDL used for implementation of themodeled block. SecureIP is an IP encryption methodology. To support SecureIP models, aVerilog LRM - IEEE Std 1364-2005 encryption compliant simulator is required. A mixed-language simulator for VHDL simulation.SecureIP models use a Verilog standard. To use them in a VHDL design, a mixed-languagesimulator is required. The simulator must be able to simulate VHDL and Verilogsimultaneously. An installed GTP transceiver SecureIP model. The correct setup of the simulator for SecureIP use (initialization file, environment variables). The ability to run COMPXLIB, which compiles the simulation libraries (e.g., UNISIM,SIMPRIMS) in the correct order. The correct simulator resolution (Verilog). The user guide of the simulator and UG626, Synthesis and Simulation Design Guide provide adetailed list of settings for SecureIP support.7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016www.xilinx.comSend Feedback17

Chapter 1:Transceiver and Tool OverviewPorts and AttributesThere are no simulation-only ports on the GTPE2 COMMON and GTPE2 CHANNEL primitives.GTPE2 COMMON AttributesThe GTPE2 COMMON primitive has attributes intended only for simulation. Table 1-2 lists thesimulation-only attributes of the GTPE2 COMMON primitive. The names of these attributes startwith SIM .Table 1-2:GTPE2 COMMON Simulation-Only AttributesAttribute18TypeDescriptionSIM PLL0REFCLK SEL3-bitBinaryThis attribute selects the reference clock sourceused to drive PLL0 in simulation for designs wherePLL0 is always driven by the same reference clocksource. SIM PLL0REFCLK SEL allows forsimulation before and after the port swap changes.This allows for the block to be simulated with thecorrect clock source both before and after the portswap. SIM PLL0REFCLK SEL must be set to thesame value as PLL0REFCLK SEL

UG482 (v1.9) December 19, 2016 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide 10/23/2012 1.3 Added Artix-7 device in Functional Description, page 25, Single External Reference Clock Use Model, page 32, and Multiple External Reference Clock Use Model, page 33. Deleted XC7A350T in Figure 3-4 and Figure 3-5 footnotes.