Zynq 7000 SoC (Z 7007S, Z 7012S, Z 7014S, Z 7010, Z 7015, And Z 7020 .

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Zynq‐7000 SoC(Z‐7007S, Z‐7012S, Z‐7014S, Z‐7010, Z‐7015, and Z‐7020):DC and AC Switching CharacteristicsDS187 (v1.21) December 1, 2020Product SpecificationIntroductionThe Zynq -7000 SoCs are available in -3, -2, -1, and -1LIspeed grades, with -3 having the highest performance. The-1LI devices can operate at either of two programmablelogic (PL) VCCINT/VCCBRAM voltages, 0.95V and 1.0V, and arescreened for lower maximum static power. The speedspecification of a -1LI device is the same as the -1 speedgrade. When operated at PL VCCINT/VCCBRAM 0.95V, the-1LI static and dynamic power is reduced. Zynq-7000 deviceDC and AC characteristics are specified in commercial,extended, industrial and expanded (Q-temp) temperatureranges. Except for the operating temperature range orunless otherwise noted, all the DC and AC electricalparameters are the same for a particular speed grade (thatis, the timing characteristics of a -1 speed grade industrialdevice are the same as for a -1 speed grade commercialdevice). However, only selected speed grades and/ordevices are available in the commercial, extended,industrial, or Q-temp temperature ranges.All supply voltage and junction temperature specificationsare representative of worst-case conditions. The parametersincluded are common to popular designs and typicalapplications.The available device/package combinations are outlined in: Zynq-7000 SoC Overview (DS190) XA Zynq-7000 SoC Overview (DS188) Defense-grade Zynq-7000Q SoC Overview (DS196)This Zynq-7000 SoC data sheet, which covers thespecifications for the XC7Z007S, XC7Z012S, XC7Z014S,XC7Z010, XA7Z010, XC7Z015, XC7Z020, XA7Z020, andXQ7Z020, complements the Zynq-7000 SoC documentationsuite available on the Xilinx website at www.xilinx.com/zynq.DC CharacteristicsTable 1: Absolute Maximum Ratings(1)SymbolDescriptionMinMaxUnitsProcessing System (PS)VCCPINTPS internal logic supply voltage–0.51.1VVCCPAUXPS auxiliary supply voltage–0.52.0VVCCPLLPS PLL supply–0.52.0VVCCO DDRPS DDR I/O supply voltage–0.52.0VVCCO MIO(2)PS MIO I/O supply voltage–0.53.6VVPREFPS input reference voltage–0.52.0VPS MIO I/O input voltage–0.40VCCO MIO 0.55VPS DDR I/O input voltage–0.55VCCO DDR 0.55VVPIN(2)(3)(4)(5)Programmable Logic (PL)VCCINTPL internal supply voltage–0.51.1VVCCAUXPL auxiliary supply voltage–0.52.0VVCCBRAMPL supply voltage for the block RAM memories–0.51.1VVCCOPL supply voltage for HR I/O banks–0.53.6VVREFInput reference voltage–0.52.0V Copyright 2011–2020 Xilinx, Inc. Xilinx, the Xilinx logo, Zynq, Virtex, Artix, Kintex, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinxin the United States and other countries. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex, PrimeCell, Mali, and MPCore are trademarks of Arm Limited in the EUand other countries. All other trademarks are the property of their respective owners.DS187 (v1.21) December 1, 2020Product Specificationwww.xilinx.comSend Feedback1

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)Table 1: Absolute Maximum Ratings(1) (Cont’d)SymbolDescriptionMinMaxUnitsI/O input voltage for HR I/O banks–0.40VCCO 0.55VVIN(3)(4)(5)I/O input voltage (when VCCO 3.3V) for VREF and differential I/O standardsexcept TMDS 33(6)–0.402.625VVCCBATTKey memory battery backup supply–0.52.0VGTP Transceiver (XC7Z012S and XC7Z015 Only)VMGTAVCCAnalog supply voltage for the GTP transmitter and receiver circuits–0.51.1VVMGTAVTTAnalog supply voltage for the GTP transmitter and receiver terminationcircuits–0.51.32VVMGTREFCLKReference clock absolute input voltage–0.51.32VVINReceiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage–0.51.26VIDCIN-FLOATDC input current for receiver input pins DC coupled RX termination floating–14mAIDCIN-MGTAVTTDC input current for receiver input pins DC coupled RXtermination VMGTAVTT–12mAIDCIN-GNDDC input current for receiver input pins DC coupled RX termination GND–6.5mAIDCOUT-FLOATDC output current for transmitter pins DC coupled RX termination floating–14mAIDCOUT-MGTAVTTDC output current for transmitter pins DC coupled RXtermination VMGTAVTT–12mAXADCVCCADCXADC supply relative to GNDADC–0.52.0VVREFPXADC reference input relative to GNDADC–0.52.0V–65150 C– 220 C– 260 C– 125 CTemperatureTSTGTSOLTjStorage temperature (ambient)Maximum soldering temperature for Pb/Sn componentbodies(7)Maximum soldering temperature for Pb-free componentMaximum .Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.Applies to both MIO supply banks VCCO MIO0 and VCCO MIO1.The lower absolute voltage specification always applies.For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) or the Zynq-7000 SoC Technical Reference Manual(UG585).The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4.See Table 11 for TMDS 33 specifications.For soldering guidelines and thermal considerations, see the Zynq-7000 SoC Packaging and Pinout Specification (UG865).Table 2: Recommended Operating CCPINTPS internal logic supply voltage0.951.001.05VVCCPAUXPS auxiliary supply voltage1.711.801.89VVCCPLLPS PLL supply1.711.801.89VVCCO DDRPS DDR I/O supply voltage1.14–1.89VVCCO MIO(3)PS MIO I/O supply voltage for MIO banks1.71–3.465VDS187 (v1.21) December 1, 2020Product Specificationwww.xilinx.comSend Feedback2

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)Table 2: Recommended Operating Conditions(1)(2) (Cont’d)SymbolVPIN(4)DescriptionMinTypMaxUnitsPS DDR and MIO I/O input voltage–0.20–VCCO DDR 0.20VCCO MIO 0.20VPL internal supply voltage0.951.001.05VPL -1LI (0.95V) internal supply voltage0.920.950.98VPL auxiliary supply voltage1.711.801.89VPL block RAM supply voltage0.951.001.05VPL -1LI (0.95V) block RAM supply voltage0.920.950.98VPL supply voltage for HR I/O banks1.14–3.465VI/O input voltage–0.20–VCCO 0.20VI/O input voltage (when VCCO 3.3V) for VREF and differential I/Ostandards except TMDS (5)VCCAUXVCCBRAM(5)VCCO(6)(7)VIN(4)IIN(9)Maximum current through any (PS or PL) pin in a powered or unpoweredbank when forward biasing the clamp diodeVCCBATT(10)Battery voltageGTP Transceiver (XC7Z012S and XC7Z015 Only)VMGTAVCC(11)Analog supply voltage for the GTP transmitter and receiver circuits0.971.01.03VVMGTAVTT(11)Analog supply voltage for the GTP transmitter and receiver terminationcircuits1.171.21.23VVCCADCXADC supply relative to GNDADC1.711.801.89VVREFPExternally supplied reference voltage1.201.251.30VJunction temperature operating range for commercial (C) temperaturedevices0–85 CJunction temperature operating range for extended (E) temperaturedevices0–100 CJunction temperature operating range for industrial (I) temperaturedevices–40–100 CJunction temperature operating range for expanded (Q) temperaturedevices–40–125 l voltages are relative to ground. The PL and PS share a common ground.For the design of the power distribution system consult the Zynq-7000 SoC PCB Design Guide (UG933).Applies to both MIO supply banks VCCO MIO0 and VCCO MIO1.The lower absolute voltage specification always applies.VCCINT and VCCBRAM should be connected to the same supply.Configuration data is retained even if VCCO drops to 0V.Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.3V at 5%.See Table 11 for TMDS 33 specifications.A total of 200 mA per PS or PL bank should not be exceeded.VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX.Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTP Transceiver User Guide (UG482).DS187 (v1.21) December 1, 2020Product Specificationwww.xilinx.comSend Feedback3

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)Table 3: DC Characteristics Over Recommended Operating Data retention VCCINT voltage (below which configuration data might be lost)0.75––VVDRIData retention VCCAUX voltage (below which configuration data might be lost)1.5––VIREFPS DDR VREF 0/1, PS MIO VREF, and VREF leakage current per pin––15µAILInput or output leakage current per pin (sample-tested)––15µAPL die input capacitance at the pad––8pFPS die input capacitance at the pad––8pFPad pull-up (when selected) @ VIN 0V, VCCO 3.3V90–330µAPad pull-up (when selected) @ VIN 0V, VCCO 2.5V68–250µAPad pull-up (when selected) @ VIN 0V, VCCO 1.8V34–220µAPad pull-up (when selected) @ VIN 0V, VCCO 1.5V23–150µAPad pull-up (when selected) @ VIN 0V, VCCO 1.2V12–120µAPad pull-down (when selected) @ VIN 3.3V68–330µAPad pull-down (when selected) @ VIN 1.8V45–180µAICCADCAnalog supply current, analog circuits in powered up state––25mAIBATT(3)Battery supply current––150nAThevenin equivalent resistance of programmable input termination to VCCO/2(UNTUNED SPLIT 40)284055 Thevenin equivalent resistance of programmable input termination to VCCO/2(UNTUNED SPLIT 50)355065 Thevenin equivalent resistance of programmable input termination to VCCO/2(UNTUNED SPLIT 60)446083 nTemperature diode ideality factor–1.010––rTemperature diode series resistance–2– CIN(2)CPIN(2)IRPUIRPDRIN TERM(4)Notes:1.2.3.4.Typical values are specified at nominal voltage, 25 C.This measurement represents the die capacitance at the pad, not including the package.Maximum value specified for worst case process at 25 C.Termination resistance to a VCCO/2 level.DS187 (v1.21) December 1, 2020Product Specificationwww.xilinx.comSend Feedback4

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for PS I/O and PL HR I/O Banks(1)(2)AC Voltage Overshoot% of UI @–40 C to 125 CVCCO 0.55AC Voltage Undershoot% of UI @–40 C to 125 O 0.6046.6–0.604.77VCCO 0.6521.2–0.652.10VCCO 0.709.75–0.700.94VCCO 0.754.55–0.750.43VCCO 0.802.15–0.800.20VCCO 0.851.02–0.850.09VCCO 0.900.49–0.900.04VCCO 0.950.24–0.950.02Notes:1.2.A total of 200 mA per bank should not be exceeded.The peak voltage of the overshoot or undershoot, and the duration above VCCO 0.20V or below GND –0.20V, must not exceed the valuesin this table.Table 5: Typical Quiescent Supply CurrentSymbolICCPINTQICCPAUXQDescriptionPS quiescent VCCPINT supply currentPS quiescent VCCPAUX supply currentDS187 (v1.21) December 1, 2020Product SpecificationDeviceSpeed /A13N/AmAXQ7Z020N/A131311mAwww.xilinx.comSend Feedback5

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)Table 5: Typical Quiescent Supply Current ionPS quiescent VCCO DDR supply currentPL quiescent VCCINT supply currentPL quiescent VCCAUX supply currentPL quiescent VCCO supply currentDS187 (v1.21) December 1, 2020Product SpecificationDeviceSpeed N/A3N/AmAXQ7Z020N/A333mAwww.xilinx.comSend Feedback6

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)Table 5: Typical Quiescent Supply Current (Cont’d)SymbolICCBRAMQDescriptionPL quiescent VCCBRAM supply currentDeviceSpeed Typical values are specified at nominal voltage, 85 C junction temperatures (Tj) with single-ended SelectIO resources.Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state andfloating.The Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) estimates operating current. When therequired power-on current exceeds the estimated operating current, XPE can display the power-on current.The first value is at 0.95V, and the second value is at 1.0V.DS187 (v1.21) December 1, 2020Product Specificationwww.xilinx.comSend Feedback7

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)PS Power‐On/Off Power Supply SequencingThe recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO MIO0,VCCO MIO1, and VCCO DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. ThePS POR B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO MIO0 havereached minimum operating levels to ensure PS eFUSE integrity. For additional information about PS POR B timingrequirements refer to Resets.The recommended power-off sequence is the reverse of the power-on sequence. If VCCPAUX, VCCPLL, and the PS VCCO supplies(VCCO MIO0, VCCO MIO1, and VCCO DDR) have the same recommended voltage levels, then they can be powered by the samesupply and ramped simultaneously. Xilinx recommends powering VCCPLL with the same supply as VCCPAUX, with an optionalferrite bead filter. Before VCCPINT reaches 0.80V at least one of the four following conditions is required during the power-offstage: the PS POR B input is asserted to GND, the reference clock to the PS CLK input is disabled, VCCPAUX is lower than0.70V, or VCCO MIO0 is lower than 0.90V. The condition must be held until VCCPINT reaches 0.40V to ensure PS eFUSE integrity.For VCCO MIO0 and VCCO MIO1 voltages of 3.3V: The voltage difference between VCCO MIO0 /VCCO MIO1 and VCCPAUX must not exceed 2.625V for longer thanTVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels. The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.PL Power‐On/Off Power Supply SequencingThe recommended power-on sequence for the PL is VCCINT, VCCBRAM, VCCAUX, and VCCO to achieve minimum current drawand ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-onsequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supplyand ramped simultaneously. If VCCAUX and VCCO have the same recommended voltage levels then both can be powered bythe same supply and ramped simultaneously.For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0: The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for eachpower-on/off cycle to maintain device reliability levels. The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.GTP Transceivers (XC7Z012S and XC7Z015 Only)The recommended power-on sequence to achieve minimum current draw for the GTP transceivers (XC7Z012S and XC7Z015only) is VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. Both VMGTAVCC and VCCINT can be rampedsimultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimumcurrent draw.If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications duringpower-up and power-down. When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT – VMGTAVCC 150 mV and VMGTAVCC 0.7V, the VMGTAVTTcurrent draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can beup to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down. When VMGTAVTT is powered before VCCINT and VMGTAVTT – VCCINT 150 mV and VCCINT 0.7V, the VMGTAVTT currentdraw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down.There is no recommended sequence for supplies not shown.PS—PL Power SequencingThe PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO DDR, VCCO MIO0, andVCCO MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to preventdamage.DS187 (v1.21) December 1, 2020Product Specificationwww.xilinx.comSend Feedback8

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)Power Supply RequirementsTable 6 shows the minimum current, in addition to ICCQ, that is required by Zynq-7000 devices for proper power-on andconfiguration. If the current minimums shown in Table 5 and Table 6 are met, the device powers on after all four PL supplieshave passed through their power-on reset threshold voltages. The Zynq-7000 device must not be configured until afterVCCINT is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download atwww.xilinx.com/power) to estimate current drain on these supplies.Table 6: Power-On Current for Zynq-7000 NICCAUXMINICCOMINICCBRAMMINUnitsXC7Z007S 100 mAIICCPINTQ 70 ICCPAUXQ 40 CCDDRQper bankICCINTQ 40ICCAUXQ 60ICCOQ 90 mAICCBRAMQ 40per bankmAXC7Z012S 100 mAIICCINTQ 130ICCPINTQ 70 ICCPAUXQ 40 CCDDRQper bankICCAUXQ 60ICCOQ 90 mAICCBRAMQ 40per bankmAXC7Z014SI 100 mAICCPINTQ 70 ICCPAUXQ 40 CCDDRQper bankICCINTQ 70ICCAUXQ 60ICCOQ 90 mAICCBRAMQ 40per bankmAXC7Z010XA7Z010I 100 mAICCPINTQ 70 ICCPAUXQ 40 CCDDRQper bankICCINTQ 40ICCAUXQ 60ICCOQ 90 mAICCBRAMQ 40per bankmAXC7Z015I 100 mAICCPINTQ 70 ICCPAUXQ 40 CCDDRQICCINTQ 130per bankICCAUXQ 60ICCOQ 90 mAICCBRAMQ 40per bankmAXC7Z020XA7Z020XQ7Z020I 100 mAICCPINTQ 70 ICCPAUXQ 40 CCDDRQper bankICCAUXQ 60ICCOQ 90 mAICCBRAMQ 40per bankmAICCINTQ 70Table 7: Power Supply Ramp Ramp time from GND to 90% of VCCPINT0.250msTVCCPAUXRamp time from GND to 90% of VCCPAUX0.250msTVCCO DDRRamp time from GND to 90% of VCCO DDR0.250msTVCCO MIORamp time from GND to 90% of VCCO MIO0.250msTVCCINTRamp time from GND to 90% of VCCINT0.250msTVCCORamp time from GND to 90% of VCCO0.250msTVCCAUXRamp time from GND to 90% of VCCAUX0.250msTVCCBRAMRamp time from GND to 90% of VCCBRAMmsTVCCO2VCCAUXAllowed time per power cycle for VCCO – VCCAUX 2.625Vand VCCO MIO – VCCPAUX 2.625V0.250Tj 125 C(1)–300Tj 100 C(1)–50085 C(1)–800Tj msTMGTAVCCRamp time from GND to 90% of VMGTAVCC0.250msTMGTAVTTRamp time from GND to 90% of VMGTAVTT0.250msNotes:1.Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with worst case VCCO of 3.465V.DS187 (v1.21) December 1, 2020Product Specificationwww.xilinx.comSend Feedback9

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)DC Input and Output LevelsValues for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommendedoperating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that allstandards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOHvoltage levels shown. Other standards are sample tested.PS I/O LevelsTable 8: PS DC Input and Output Levels(1)VOLVOHIOLIOHV, MaxV, MinmAmA–0.300 35% VCCO MIO 65% VCCO MIO VCCO MIO 0.3000.450VCCO MIO – 0.4508–8LVCMOS25–0.3000.7001.700VCCO MIO 0.3000.400VCCO MIO – CCO MIO – 0.4008–8MIOHSTL I 18–0.300 VPREF – 0.100 VPREF 0.100 VCCO MIO 0.3000.400VCCO MIO – V, MinV, MaxV, MinV, MaxDDR SSTL18 I–0.300 VPREF – 0.125 VPREF 0.125 VCCO DDR 0.300 VCCO DDR/2 – 0.470 VCCO DDR/2 0.470DDR SSTL15–0.300 VPREF – 0.100 VPREF 0.100 VCCO DDR 0.300 VCCO DDR/2 – 0.175 VCCO DDR/2 0.175 13.0 –13.0DDR SSTL135–0.300 VPREF – 0.090 VPREF 0.090 VCCO DDR 0.300 VCCO DDR/2 – 0.150 VCCO DDR/2 0.150 13.0 –13.0DDR HSUL 12–0.300 VPREF – 0.130 VPREF 0.130 VCCO DDR 0.30020% VCCO DDR80% VCCO DDR0.1–0.1Notes:1.Tested according to relevant specifications.Table 9: PS Complementary Differential DC Input and Output LevelsBankI/O StandardVICM(1)VID(2)V, Min V,Typ V, Max V,Min V, MaxDDR DIFF HSUL 120.3000.6000.8500.100–DDR DIFF SSTL1350.3000.6751.0000.100–DDR DIFF SSTL150.3000.7501.1250.100DDR DIFF SSTL18 I0.3000.9001.4250.100VOL(3)VOH(4)V, MaxV, Min20% VCCO80% VCCOIOLIOHmA, Max mA, Min0.100–0.100(VCCO DDR/2) – 0.150 (VCCO DDR/2) 0.15013.0–13.0–(VCCO DDR/2) – 0.175 (VCCO DDR/2) 0.17513.0–13.0–(VCCO DDR/2) – 0.470 (VCCO DDR/2) 0.4708.00–8.00Notes:1.2.3.4.VICM is the input common mode voltage.VID is the input differential voltage (Q–Q).VOL is the single-ended low-output voltage.VOH is the single-ended high-output voltage.DS187 (v1.21) December 1, 2020Product Specificationwww.xilinx.comSend Feedback10

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)PL I/O LevelsTable 10: SelectIO DC Input and Output Levels(1)(2)I/O StandardVILVIHVOLVOHIOLIOHV, MinV, MaxV, MinV, MaxV, MaxV, MinmAmAHSTL I–0.300VREF – 0.100VREF 0.100VCCO 0.3000.400VCCO – 0.4008.00–8.00HSTL I 18–0.300VREF – 0.100VREF 0.100VCCO 0.3000.400VCCO – 0.4008.00–8.00HSTL II–0.300VREF – 0.100VREF 0.100VCCO 0.3000.400VCCO – 0.40016.00–16.00HSTL II 18–0.300VREF – 0.100VREF 0.100VCCO 0.3000.400VCCO – 0.40016.00–16.00HSUL 12–0.300VREF – 0.130VREF 0.130VCCO 0.30020% VCCO80% VCCO0.10–0.10LVCMOS12–0.30035% VCCO65% VCCOVCCO 0.3000.400VCCO – 0.400Note 3Note 3LVCMOS15–0.30035% VCCO65% VCCOVCCO 0.30025% VCCO75% VCCONote 4Note 4LVCMOS18–0.30035% VCCO65% VCCOVCCO 0.3000.450VCCO – 0.450Note 5Note 5LVCMOS25–0.3000.71.700VCCO 0.3000.400VCCO – 0.400Note 4Note 4LVCMOS33–0.3000.82.0003.4500.400VCCO – 0.400Note 4Note 4LVTTL–0.3000.82.0003.4500.4002.400Note 5Note 5MOBILE DDR–0.30020% VCCO80% VCCOVCCO 0.30010% VCCO90% VCCO0.10–0.10PCI33 3–0.40030% VCCO50% VCCOVCCO 0.50010% VCCO90% VCCO1.50–0.50SSTL135–0.300VREF – 0.090VREF 0.090VCCO 0.300 VCCO/2 – 0.150 VCCO/2 0.15013.00–13.00SSTL135 R–0.300VREF – 0.090VREF 0.090VCCO 0.300 VCCO/2 – 0.150 VCCO/2 0.1508.90–8.90SSTL15–0.300VREF – 0.100VREF 0.100VCCO 0.300 VCCO/2 – 0.175 VCCO/2 0.17513.00–13.00SSTL15 R–0.300VREF – 0.100VREF 0.100VCCO 0.300 VCCO/2 – 0.175 VCCO/2 0.1758.90–8.90SSTL18 I–0.300VREF – 0.125VREF 0.125VCCO 0.300 VCCO/2 – 0.470 VCCO/2 0.4708.00–8.00SSTL18 II–0.300VREF – 0.125VREF 0.125VCCO 0.300 VCCO/2 – 0.600 VCCO/2 0.60013.40–13.40Notes:1.2.3.4.5.6.Tested according to relevant specifications.3.3V and 2.5V standards are only supported in HR I/O banks.Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks.For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471).Table 11: Differential SelectIO DC Input and Output LevelsI/O StandardBLVDS 25VICM(1)VID(2)VOCM(3)V, Min V, Typ V, Max V, Min V, Typ V, Max0.3001.2001.4250.100VOD(4)V, MinV, TypV, MaxV, Min V, Typ V, MaxNote 5–––1.250–MINI LVDS 25 0.3001.200 VCCAUX 0.2000.4000.6001.0001.2001.4000.3000.4500.600PPDS 250.2000.900 VCCAUX 0.1000.2500.4000.5000.9501.4000.1000.2500.400RSDS 000.3500.600TMDS 332.7002.9653.2300.1500.6751.200VCCO–0.405 VCCO–0.300 VCCO–0.190 0.4000.6000.800Notes:1.2.3.4.5.6.VICM is the input common mode voltage.VID is the input differential voltage (Q–Q).VOCM is the output common mode voltage.VOD is the output differential voltage (Q–Q).VOD for BLVDS will vary significantly depending on topology and loading.LVDS 25 is specified in Table 13.DS187 (v1.21) December 1, 2020Product Specificationwww.xilinx.comSend Feedback11

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)Table 12: Complementary Differential SelectIO DC Input and Output LevelsI/O StandardVICM(1)VID(2)V, Min V,Typ V, Max V,Min V, MaxVOL(3)VOH(4)IOLIOHV, MaxV, MinmA, MaxmA, MinDIFF HSTL 00DIFF HSTL I .00DIFF HSTL 16.00DIFF HSTL II 16.00DIFF HSUL 120.3000.6000.8500.100–20% VCCO80% VCCO0.100–0.100DIFF MOBILE DDR 0.3000.9001.4250.100–10% VCCO90% VCCO0.100–0.100DIFF SSTL1350.3000.6751.0000.100–(VCCO/2) – 0.150(VCCO/2) 0.15013.0–13.0DIFF SSTL135 R0.3000.6751.0000.100–(VCCO/2) – 0.150(VCCO/2) 0.1508.9–8.9DIFF SSTL150.3000.7501.1250.100–(VCCO/2) – 0.175(VCCO/2) 0.17513.0–13.0DIFF SSTL15 R0.3000.7501.1250.100–(VCCO/2) – 0.175(VCCO/2) 0.1758.9–8.9DIFF SSTL18 I0.3000.9001.4250.100–(VCCO/2) – 0.470(VCCO/2) 0.4708.00–8.00DIFF SSTL18 II0.3000.9001.4250.100–(VCCO/2) – 0.600(VCCO/2) 0.60013.4–13.4Notes:1.2.3.4.VICM is the input common mode voltage.VID is the input differential voltage (Q–Q).VOL is the single-ended low-output voltage.VOH is the single-ended high-output voltage.LVDS DC Specifications (LVDS 25)Table 13: LVDS 25 DC Specifications(1)SymbolDC OSupply voltageVOHOutput High voltage for Q and QRT 100 across Q and Q signals––1.675VVOLOutput Low voltage for Q and QRT 100 across Q and Q signals0.700––VVODIFFDifferential output voltage:(Q – Q), Q High(Q – Q), Q HighRT 100 across Q and Q signals247350600mVVOCMOutput common-mode voltageRT 100 across Q and Q signals1.001.251.425VVIDIFFDifferential input voltage:(Q – Q), Q High(Q – Q), Q High100350600mVVICMInput common-mode voltage0.31.21.500VNotes:1.Differential inputs for LVDS 25 can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the7 Series FPGAs SelectIO Resources User Guide (UG471) for more information.DS187 (v1.21) December 1, 2020Product Specificationwww.xilinx.comSend Feedback12

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)AC Switching CharacteristicsAll values represented in this data sheet are based on the speed specifications in the ISE Design Suite 14.7 andVivado Design Suite 2016.3 as outlined in Table 14.Table 14: Zynq-7000 SoC Speed Specification Version By DeviceISE 14.7Vivado 2016.3Device1.081.11XC7Z010 and XC7Z020N/A1.11XC7Z007S, XC7Z012S, XC7Z014S, and XC7Z0151.061.09XA7Z010 and XA7Z0201.061.10XQ7Z020Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, orProduction. Each designation is defined as follows:Advance Product SpecificationThese specifications are based on simulations only and are typically available soon after device design specifications arefrozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reportingmight still occur.Preliminary Product SpecificationThese specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades withthis designation are intended to give a better indication of the expected performance of production silicon. The probabilityof under-reporting delays is greatly reduced as compared to Advance data.Production Product SpecificationThese specifications are released once enough production silicon of a particular device family member has beencharacterized to provide full correlation between specifications and devices over numerous production lots. There is nounder-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowestspeed grades transition to Production before faster speed grades.Testing of AC Switching CharacteristicsInternal timing parameters are derived from measuring internal test patterns. All AC switching characteristics arerepresentative of worst-case supply voltage and junction temperature conditions.For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer andback-annotate to the simulation net list. Unless otherwise noted, values apply to all Zynq-7000 devices.Speed Grade DesignationsSince individual family members are produced at different times, the migration from one category to another dependscompletely on the status of the fabrication process for each device. Table 15 correlates the current status of each Zynq-7000device on a per speed grade basis.Table 15: Zynq-7000 Device Speed Grade DesignationsDeviceSpeed Grade E, -2I, -1C, -1IXC7Z012S-2E, -2I, -1C, -1IXC7Z014S-2E, -2I, -1C, -1IXC7Z010-3E, -2E, -2I, -1C, -1I, -1LIXC7Z015-3E, -2E, -2I, -1C, -1I, -1LIDS187 (v1.21) December 1, 2020Product Specificationwww.xilinx.comSend Feedback13

Zynq-7000 SoC (Z-7

4. For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) or the Zynq-7000 SoC Technical Reference Manual (UG585). 5. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4. 6. See Table 11 for TMDS_33 specifications. 7.