Zynq-7000 All Programmable SoC Packaging And Pinout Product .

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Zynq-7000All Programmable SoCPackaging and PinoutProduct SpecificationUG865 (v1.6) March 1, 2016

Notice of DisclaimerThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximumextent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIESAND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, includingnegligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with,the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if suchdamage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correctany errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce,modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditionsof Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP cores may besubject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to befail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in suchcritical applications, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos.Automotive Applications DisclaimerXILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFEPERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS AFAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THEREDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONALINJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. Copyright 2012–2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brandsincluded herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respectiveowners.Zynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016www.xilinx.comSend Feedback2

Revision HistoryThe following table shows the revision history for this document.DateVersionRevision05/08/20121.0Initial Xilinx release.09/24/20121.1Added the CLG225 throughout document.Clarified RSVDVCC[3:1] and PS MIO VREF in Table 1-5, page 12. Added Note 9 tothe DXN 0 description.Chapter 3: Updated the legends for the pinout diagrams.Chapter 4: Added mechanical drawings.02/14/20131.2Updated VCCPLL in Table 1-5 and added Note 2.Updated Figure 3-8 and Figure 3-16.Revised Figure 4-1, increased the A and A2 maximum dimensions. UpdatedFigure 4-11. Added Figure 4-6, Figure 4-7. Figure 4-9, and Figure 4-12.In Table 5-1, updated thermal resistance data for the XC7Z010 and XC7Z020devices.Updated Appendix B, Heat Sink Guidelines for Lidless Flip-Chip Packages.11/12/20131.3Added the CLG485, SBG485, and FFG1156 packages. Added the XC7Z015 andXC7Z100 devices. Added the XA Zynq-7000 AP SoC devices (XA7Z010 andXA7Z020). Added the Zynq-7000Q AP SoC devices (XQ7Z020, XQ7Z030, andXQ7Z045) and the RF484 and RF676 packages. Updated the Notice of Disclaimer.Clarified the maximum and available PS I/O pins as 128 in Table 1-1 and Table 1-4.In Table 1-5, updated the PUDC B description.Added Note 1 and updated the data in Table 5-1. Updated the Pb-Free ReflowSoldering in Chapter 5 discussion. Updated the MSL for flip-chip packages inTable 5-3.Removed the engineering sample notation from the top mark drawings inFigure 6-1.Updated Appendix A, Recommended PCB Design Rules.06/11/20141.4Added the RF900 package for the XQ7Z045 to Table 1-1, Table 1-3, Table 1-4,Table 2-1, Table 3-1, Figure 3-45, Figure 3-46, Figure 3-47, Figure 3-48,Figure 4-17, and Table 5-1.Updated the XC7Z015 bank numbering (Figure 1-2).Added XA7Z030 to Table 1-3, Table 1-4, Table 2-1, Table 3-1, Figure 1-4,Figure 3-25, Figure 3-26, Figure 3-27, Figure 3-28, Figure 4-6, Figure 4-7, andTable 5-1.Updated the PUDC B and PS MIO VREF descriptions in Table 1-5. Added theGTP/GTX XY coordinates to Figure 1-2, Figure 1-4, Figure 1-5, and Figure 1-6.In Chapter 3, updated the memory groupings legend’s DCI pin descriptions.Added the Heat Sink Removal Procedure and Package Pressure Handling Capacitysections. For clarity, updated Figure 5-7 and Table 5-3 with specific deviceinformation.Added Chapter 7, Packing and Shipping.Zynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016www.xilinx.comSend Feedback3

DateVersionRevision11/17/20141.5Added the XC7Z035 device throughout the specification. Added a discussion onULA materials on page 7. Added Note on page 28. Updated Figure 5-4: ThermalManagement Options for Flip-Chip BGA Packages. In Table 5-2 and Figure 5-7,revised the peak temperature (body) values and the ramp-up rate and ramp-downrate to 2 C/s. Updated the Peak Package Reflow Body Temperature values inTable 5-3 and added Note 1. Updated Soldering Guidelines section. Added PostReflow/Cleaning/Washing and Conformal Coating sections. Updated References.03/01/20161.6Updated to add RF1156 packages and RoHS compliant options (FFV packages)where applicable.In Table 1-5, updated the PS POR B and SRCC descriptions.Added the XC7Z035 in the FF/FFG/FFV900 package to Table 1-6.Updated many of the drawings in Chapter 4. Replaced the FF/FFG/FFV1156 packagemechanical drawing in Figure 4-14.Completely revised Chapter 5, Thermal Specifications with industry standardguidelines for all sections. Updated the Thermal Interface Material sectionpreviously in Appendix B, and added the Applied Pressure from Heat Sink to thePackage via Thermal Interface Materials.In Appendix B: Moved the Reasons for Thermal Interface Material section toChapter 5. Removed the Package Loading Specifications section.Zynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016www.xilinx.comSend Feedback4

Table of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Chapter 1: Package OverviewSummary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Device/Package Combinations and Maximum I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Pin Compatibility Between Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Die Level Bank Numbering Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Chapter 2: Zynq-7000 AP SoC Package FilesAbout ASCII Package Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26ASCII Pinout Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Chapter 3: Device DiagramsSummary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Zynq-7000 AP SoC Device Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Chapter 4: Mechanical DrawingsSummary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74CLG225 Wire-Bond Chip-Scale BGA(XC7Z010 and XA7Z010) (0.8 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76CLG400 (XC7Z010, XA7Z010, XC7Z020, and XA7Z020) and CL400 (XQ7Z020) Wire-Bond Chip-ScaleBGA (0.8 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77CLG484 (XC7Z020, XA7Z020), CL484 (XQ7Z020) and CLG485 (XC7Z015) Wire-Bond Chip-Scale BGA(0.8 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78SBG485/SBV485 (XC7Z030) Flip-Chip Lidless BGA (0.8 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . 79FBG484/FBV484 (XC7Z030, XA7Z030, and XQ7Z030) Flip-Chip Lidless BGA (1.0 mm Pitch). . . . . . 81FBG676/FBV676 (XC7Z030, XC7Z035, and XC7Z045) Flip-Chip Lidless BGA (1.0 mm Pitch) . . . . . . 83FFG676/FFV676 (XC7Z030) Flip-Chip BGA(1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86FFG676/FFV676 Flip-Chip BGA(XC7Z035 and XC7Z045)(1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87FFG900/FFV900 (XC7Z035, XC7Z045, and XC7Z100) Flip-Chip BGA (1.0 mm Pitch) . . . . . . . . . . . . 88Zynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016www.xilinx.comSend Feedback5

FFG1156/FFV1156 (XC7Z100)Flip-Chip BGA (1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RB484 Ruggedized Flip-Chip BGA (XQ7Z030)(1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RF676 (XQ7Z030 and XQ7Z045) andRFG676 (XQ7Z045) Ruggedized Flip-Chip BGA(1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RF900 (XQ7Z045 and XQ7Z100)Ruggedized Flip-Chip BGA (1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RF1156 (XQ7Z100) Ruggedized Flip-Chip BGA(1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8990919293Chapter 5: Thermal SpecificationsSummary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Support for Compact Thermal Models (CTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Thermal Management Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Thermal Interface Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Soldering Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Chapter 6: Package MarkingMarking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Chapter 7: Packing and ShippingIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Appendix A: Recommended PCB Design RulesBGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Appendix B: Heat Sink Guidelines for Lidless Flip-Chip PackagesHeat Sink Attachments for Lidless Flip-chip BGA (FB/FBG/FBV) . . . . . . . . . . . . . . . . . . . . . . . . . . 114Types of Heat Sink Attachments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Appendix C: Additional ResourcesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Zynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016www.xilinx.comSend Feedback6

Chapter 1Package OverviewSummaryThis chapter covers the following topics: Introduction Device/Package Combinations and Maximum I/Os Pin Definitions Pin Compatibility Between Packages Die Level Bank Numbering OverviewIntroductionThis section describes the pinouts for the Zynq -7000 All Programmable (AP) SoC availablein 0.8 mm pitch wire bond and various 0.8 mm and 1.0 mm pitch flip-chip and fine-pitchBGA packages.Package inductance is minimized as a result of optimal placement and even distribution aswell as an optimal number of Power and GND pins.Flip-chip packages (FFG, FBG, SBG, RFG) are RoHS 6 of 6 compliant, with exemption 15where there is lead in the C4 bumps that are used to complete a viable electrical connectionbetween the semiconductor die and the package substrate. Flip-chip packages (FFV, FBV,SBV) are RoHS 6 of 6 compliant without the use of exemption 15. Non-flip chip packages(CLG) are RoHS 6 of 6 compliant. Selected packages include a Pb-only option.All of the Zynq-7000 AP SoC devices supported in a particular package are pinoutcompatible.Zynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016www.xilinx.comSend Feedback7

Chapter 1:Package OverviewThe Zynq-7000 AP SoC contains a large number of fixed and flexible I/O. Zynq-7000 AP SoChas a constant 128 pins dedicated to memory interfaces (DDR I/O), multiplexed peripherals(MIO), and control. Programmable logic provides additional pins for SelectIO resources(SIO) and multi-gigabit serial transceivers (GTP or GTX) that scale by device as well as fixedpins for configuration and analog-to-digital conversion (XADC). SIO can be used to extendthe MIO to further leverage the fixed peripherals of the processing system (PS).Each device is split into I/O banks to allow for flexibility in the choice of I/O standards (seeUG471, 7 Series FPGAs SelectIO Resources User Guide). The PS I/Os are described in UG585,Zynq-7000 All Programmable SoC Technical Reference Manual. Table 1-5 providesdefinitions for all pin types.Zynq-7000 AP SoCs flip-chip assembly materials are manufactured using ultra-low alpha(ULA) materials defined as 0.002 cph/cm 2 or materials that emit less than 0.002alpha-particles per square centimeter per hour.Zynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016www.xilinx.comSend Feedback8

Chapter 1:Package OverviewDevice/Package Combinations and Maximum I/OsTable 1-1 shows the maximum number of user I/Os possible in the Zynq-7000 AP SoC BGApackages.Table 1-1:Zynq-7000 AP SoC Package SpecificationsPackage ge Pitch (mm) Size (mm)MaximumMaximumTypeSelectIO Resources(2) PS I/OsBGA0.813 x 135486BGA0.817 x 17125128BGA0.819 x 19200128CL/CLG485BGA0.819 x 19150128SBG/SBV485BGA0.819 x 19150128BGA1.023 x 23163128FB/FBG/FBV676BGA1.027 x 27250128FF/FFG/FFV676BGA1.027 x 27250128BGA1.031 x 31362128BGA1.035 x 35400128BGA1.023 x 23163128BGA1.027 x 27250128BGA1.031 x 31362128BGA1.035 x 00Wire-bondFlip-chip F1156RuggedizedFlip-Chip LidlessRuggedizedFlip-chipNotes:1. Leaded package options (CLxxx/FFxxx/FBxxx) are available. RoHS complaint options (FFG/FFV, FBG/FBV, SBG/SBV, CLG, andRFG) are described in the Introduction, page 7.2. The maximum I/O numbers do not include pins in the configuration Bank 0 (Table 1-2) or the GT serial transceivers.Zynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016www.xilinx.comSend Feedback9

Chapter 1:Package OverviewTable 1-2 lists the 17 dedicated pins.Table 1-2:Zynq-7000 AP SoC Pins in the Dedicated Configuration Bank (Bank0)DXP 0VCCBATT 0INIT B 0TDO 0TDI 0GNDADC 0DXN 0DONE 0VN 0TCK 0VREFN 0VCCADC 0VP 0TMS 0VREFP 0CFGBVS 0PROGRAM B 0Serial Transceiver Channels by Device/PackageTable 1-3 lists the quantity of GTX serial transceiver channels for most of theZynq-7000 AP SoC devices. In all devices, a serial transceiver channel is one set of MGTRXP,MGTRXN, MGTTXP, and MGTTXN pins. The XC7Z015, in the CLG485 package, has four GTPserial transceiver channels.Table 1-3:Serial Transceiver Channels by Device/PackageGTX (or GTP) Channels by PackageDeviceCL/CLG225FB/FBG/FBV484 FB/FBG/FBV676FF/FFG/FFV900 FF/FFG/FFV1156CL/CLG400 CL/CLG485 /RFG676XC7Z010XA7Z010––––––XC7Z015–4 6Zynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016www.xilinx.comSend Feedback10

Chapter 1:Package OverviewTable 1-4 shows the number of available SelectIO resources (SIO), the number of differentialSIO pairs, and the number of available PS I/Os for each Zynq-7000 AP SoC device/packagecombination. When applicable, it also lists the number of SIOs in the 3.3V-capablehigh-range (HR) banks and the number of 1.8V-capable high-performance (HP) banks.Table 1-4:Available SIO and PS I/O Pins by Device/Package CL484CLG484CLG485CL400CLG400I/O /OI/OI/OI/OI/OI/OI/OHR HPHR HPHR HPHR HPHR HPHR HPHR HPHR HP I/O54XC7Z010 User I/OXA7Z010 Differential 27086 rential –––––––XC7Z020 User I/OXA7Z020 Differential –––1250128 ––––––––––––––100 63 128 50 100 128 100 150 128––––––Differential –––––––––48User I/O–––––––––Differential ––––––––User I/O–––––––Differential ––––––User I/O–––––Differential ––––User I/O–––Differential ––User 7Z020XQ7Z030XQ7Z045XQ7Z100User I/OUser I/O2448–4872–––––––100 63 –––100 150 128 212 150 ––––––––––100 150 128 212 150 102 ––212 150 128 250 150 102 –––Differential –––––User I/O–––––––––100 63 128–––100 150 128––––––Differential ––––User 0 150 128 212 150 128–––Differential 102 72–––User ––212 150 128 250 150 128Differential –102 72Zynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016128 20029–www.xilinx.com7272––102 72–––––120 72120 72Send Feedback––11

Chapter 1:Package OverviewPin DefinitionsTable 1-5 lists the pin definitions used in Zynq-7000 AP SoC packages.Note: There are dedicated general purpose user I/O pins listed separately in Table 1-5. There arealso multi-function pins where the pin names start with either IO LXXY ZZZ # or IO XX ZZZ #,where ZZZ represents one or more functions in addition to being general purpose user I/O. If notused for their special function, these pins can be user I/O.Table 1-5:Zynq-7000 AP SoC Pin DefinitionsPin NameTypeDirectionDescriptionInput/OutputMost user I/O pins are capable of differential signalingand can be implemented as pairs. The top and bottom I/Opins are always single ended. Each user I/O is labeledIO LXXY #, where: IO indicates a user I/O pin. L indicates a differential pair, with XX a unique pair inthe bank and Y [P N] for the positive/negative sides ofthe differential pair. # indicates a bank number.User I/O PinsIO LXXY #IO XX #DedicatedConfiguration PinsFor more information about these pins, see the Configuration Pin Definitions table in UG470, 7 Series FPGAsConfiguration User Guide. See also the Boot and Configuration chapter in UG585, Zynq-7000All Programmable SoC Technical Reference Manual.DONE 0Dedicated (1)BidirectionalActive High, DONE indicates successful completion ofconfiguration.INIT B 0Dedicated (1)Bidirectional(open-drain)Active Low, indicates initialization of configurationmemory.PROGRAM B 0Dedicated (1)InputActive Low, asynchronous reset to configuration logic.TCK 0Dedicated (1)InputJTAG clock.TDI 0Dedicated (1)InputJTAG data input.TDO 0Dedicated (1)OutputJTAG data output.TMS 0Dedicated (1)InputJTAG mode select.InputThis pin selects the preconfiguration I/O standard type forthe dedicated configuration bank 0. If the VCCO for bank 0is 2.5V or 3.3V, then this pin must be connected to VCCO 0.If the VCCO for bank 0 is less than or equal to 1.8V, then thispin should be connected to GND.CFGBVS 0Dedicated (1)Note: To avoid device damage, this pin must beconnected correctly. See the Configuration Bank VoltageSelect section in UG470, 7 Series FPGAs Configuration UserGuide for more information.Zynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016www.xilinx.comSend Feedback12

Chapter 1:Table 1-5:Package OverviewZynq-7000 AP SoC Pin Definitions (Cont’d)Pin NamePUDC p During Configuration (bar)Active-Low PUDC B input enables internal pull-upresistors on the SelectIO pins after power-up and duringconfiguration. When PUDC B is Low, internal pull-up resistors areenabled on each SelectIO pin. When PUDC B is High, internal pull-up resistors aredisabled on each SelectIO pin.PUDC B must be tied either directly (or through a 1KΩ orless resistor) to VCCO 34 or GND.CAUTION! Do not allow this pin to float before andduring configuration.Power/Ground PinsGNDDedicatedN/AGround, tied common.VCCPINTDedicatedN/A1.0V logic supply for PS. Independent from PL V CCINTsupply.VCCPAUXDedicatedN/A1.8V auxiliary power supply for PS. Independent from PLV CCAUX supply.VCCO MIO0DedicatedN/A1.8V–3.3V PS I/O supply for MIO bank 500.VCCO MIO1DedicatedN/A1.8V–3.3V PS I/O supply for MIO bank 501.VCCO DDRDedicatedN/A1.2V–1.8V DDR I/O supply.VCCPLL(2)DedicatedN/A1.8V PLL supply for PS. A 0.47 µF to 4.7 µF 0402 capacitormust be placed near the VCCPLL BGA via. In addition, whenpowered by V CCPAUX, the V CCPLL must be filtered througha 120Ω at 100 MHz (size 0603) ferrite bead and a 10 µF(size 0603) decoupling capacitor to minimize PLL jitter.VCCAUXDedicatedN/A1.8V power-supply pins for auxiliary circuits.VCCAUX IO G# (3)DedicatedN/A1.8V/2.0V power-supply pins for auxiliary I/O circuits.VCCINTDedicatedN/A1.0V power-supply pins for the internal core logic.VCCO #(4)DedicatedN/APower-supply pins for the output drivers (per bank).VCCBRAMDedicatedN/A1.0V power-supply pins for the PL block RAM.VCCBATT 0DedicatedN/ADecryptor key memory backup supply; this pin should betied to the appropriate VCC or GND when not used. (5)Multi-functionN/AThese are input threshold voltage pins. They become userI/Os when an external threshold voltage is not needed(per bank).RSVDVCC[3:1]DedicatedN/AReserved pins—must be tied to V CCO 0.RSVDGNDDedicatedN/AReserved pins—must be tied to GND.VREFZynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016www.xilinx.comSend Feedback13

Chapter 1:Table 1-5:Package OverviewZynq-7000 AP SoC Pin Definitions (Cont’d)Pin NameTypeDirectionDescriptionPS MIO PinsPS POR BDedicatedInputPower on reset. The PS POR B must be asserted to GNDduring the power-on sequence until V CCPINT, V CCPAUX, andV CCO MIO0 have reached the minimum operating levelsand the PS CLK reference is within specification. Whendeasserted, the PS begins the boot process. Before VCCPINTreaches 0.80V, at least one of these four conditions isrequired during the power-off stage: The PS POR B input is asserted to GND. The reference clock to the PS CLK input is disabled. V CCPAUX is lower than 0.70V. V CCO MIO0 is lower than 0.90V.To ensure PS eFUSE integrity, the applicable conditionmust be held until V CCPINT reaches 0.40V.See the Zynq-7000 All Programmable SoC (Z-7010,Z-7015, and Z-7020) Data Sheet: DC and AC SwitchingCharacteristics (DS187) [Ref 4] andZynq-7000 All Programmable SoC (Z-7030, Z-7035,Z-7045, and Z-7100) Data Sheet: DC and AC SwitchingCharacteristics (DS191) [Ref 5] for more information onthe power-on sequence.PS CLKDedicatedInputSystem reference clock. PS CLK must be between 30 MHzand 60 MHz.PS SRST BDedicatedInputSystem reset. For use with debuggers. When 0, forces thePS to enter the system reset sequence.VoltageReferenceThe PS MIO VREF provides a reference voltage for theRGMII input receivers.If an RGMII interface is not being used, the PS MIO VREFpin can be left to float.If an RGMII interface is being used, tie this pin to a voltageequal to ½ VCCO MIO1.Example: When using a HSTL18 RGMII interface theV CCO MIO1 is set to 1.8V. The PS MIO VREF must be set to0.9V.A resistor divider can be used to generate thePS MIO VREF.See UG933, Zynq-7000 All Programmable SoC PCB DesignGuide for decoupling recommendations.PS MIO VREFPS MIO[53:0]DedicatedMultiuse I/O. Multiuse I/O can be configured to supportmultiple I/O interfaces. These interfaces include SPI andMulti-function Input/OutputQuad-SPI flash, NAND, USB, Ethernet, SDIO, UART, SPI, andGPIO interfaces.Zynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016www.xilinx.comSend Feedback14

Chapter 1:Table 1-5:Package OverviewZynq-7000 AP SoC Pin Definitions (Cont’d)Pin NameTypeDirectionDescriptionPS DDR CKPDedicatedOutputDDR differential clock positive.PS DDR CKNDedicatedOutputDDR differential clock negative.PS DDR CKEDedicatedOutputDDR clock enable.PS DDR CS BDedicatedOutputDDR chip select.PS DDR RAS BDedicatedOutputDDR RAS control signal.PS DDR CAS BDedicatedOutputDDR CAS control signal.PS DDR WE BDedicatedOutputDDR write enable signal.PS DDR BA[2:0]DedicatedOutputDDR bank address.PS DDR A[14:0]DedicatedOutputDDR row and column address.PS DDR ODTDedicatedOutputDDR termination control.PS DDR DRST BDedicatedOutputDDR reset signal for DDR3 devices.PS DDR DQ[31:0]DedicatedPS DDR DM[3:0]DedicatedPS DDR DQS P[3:0]DedicatedInput/Output DDR differential data strobe positive.PS DDR DQS N[3:0]DedicatedInput/Output DDR differential data strobe negative.PS DDR PinsPS DDR VRPInput/Output DDR data.OutputDedicatedDDR data mask.OutputDDR DCI voltage reference positive. Used to calibrate DDRI/O drive strength. Connect to a resistor to GND. The valueof the resistor should be twice the DDR termination andtrace impedance.DDR DCI voltage reference negative. Used to calibrateDDR I/O drive strength. Connect to a resistor to VCCO DDR.The value of the resistor should be twice the DDRtermination and trace impedance.PS DDR VRNDedicatedOutputPS DDR VREF[1:0]DedicatedVoltageReferenceVoltage reference for the DDR interface.Analog to Digital Converter (XADC) PinsFor more information, see the XADC Package Pins table in UG480, 7 Series FPGAs and Zynq-7000 AllProgrammable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide.VCCADC 0(6)DedicatedN/AXADC analog positive supply voltage.GNDADC 0 (6)DedicatedN/AXADC analog ground reference.VP 0(6)DedicatedInputXADC dedicated differential analog input (positive side).VN 0 (6)DedicatedInputXADC dedicated differential analog input (negative side).DedicatedN/A1.25V reference input.DedicatedN/A1.25V reference GND reference.VREFP 0 (6)VREFN0 (6)AD0P through AD15PMulti-functionAD0N through AD15NZynq-7000 AP SoC Packaging GuideUG865 (v1.6) March 1, 2016InputXADC (analog-to-digital converter) differential auxiliaryanalog inputs 0–15.www.xilinx.comSend Feedback15

Chapter 1:Table 1-5:Package OverviewZynq-7000 AP SoC Pin Definitions (Cont’d)Pin NameTypeDirectionDescriptionMulti-gigabit Serial Transceiver Pins (GTXE2 and GTPE2)For more information on the GTXE2 pins see the Pin Description and Design Guidelines section in UG476, 7 SeriesFPGAs GTX/GTH Transceivers User Guide. The GTPE2 pins are described in the Pin Description and DesignGuidelines section of UG482, 7 Series FPGAs GTP Transceivers User Guide.Positive differential receive port.MGTXRXP[0:3] orMGTPRXP[0:3]DedicatedInputMGTXRXN[0:3] orMGTPRXN[0:3]DedicatedInputMGTXTXP[0:3] orMGTPTXP[0:3]DedicatedOutputMGTXTXN[0:3] orMGTPTXN[0:3]DedicatedOutputMGTAVCC G# (7)DedicatedInput1.0V analog power-supply pin for the receiver andtransmitter internal circuits.MGTAVTT G# (7)DedicatedInput1.2V analog power-supply pin for the transmit driver.MGTVCCAUX G#(7)DedicatedInput1.8V auxiliary analog Quad PLL (QPLL) voltage supply forthe GTXE2 transceivers only.MGTREFCLK0/1PDedicatedInputPositive differential reference clock for the transceivers.MGTREFCLK0/1NDedicatedInputNegative differential reference clock for the transceivers.MGTAVTTRCALDedicatedN/APrecision reference resistor pin for internal calibrationtermination. Not used for the XC7Z010, XC7Z015, or

UG471, 7 Series FPGAs SelectIO Resources User Guide). The PS I/Os are described in UG585, Zynq-7000 All Programmable SoC Technical Reference Manual. Table 1-5 provides definitions for all pin types. UG865 (v1.6) March 1, 2016 (2) Flip-chip. Zynq-7000 AP SoC Packaging Guide www.xilinx.com