Virtex-7 T And XT FPGAs Data Sheet: DC And AC Switching . - Xilinx

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Virtex‐7 T and XT FPGAs Data Sheet:DC and AC Switching CharacteristicsDS183 (v1.29) March 23, 2021Product SpecificationIntroductionVirtex -7 T and XT FPGAs are available in -3, -2, -1, and-2L speed grades, with -3 having the highest performance.The -2L devices operate at VCCINT 1.0V and are screenedfor lower maximum static power. The speed specification ofa -2L device is the same as the -2 speed grade. The -2Gspeed grade is available in devices utilizing Stacked SiliconInterconnect (SSI) technology. The -2G speed gradesupports 12.5 Gb/s GTX or 13.1 Gb/s GTH transceivers aswell as the standard -2 speed grade specifications.Virtex-7 T and XT FPGA DC and AC characteristics arespecified in commercial, extended, industrial, and militarytemperature ranges. Except for the operating temperaturerange or unless otherwise noted, all the DC and AC electricalparameters are the same for a particular speed grade (thatis, the timing characteristics of a -1M speed grade militarydevice are the same as for a -1C speed grade commercialdevice). However, only selected speed grades and/ordevices are available in each temperature range.All supply voltage and junction temperature specificationsare representative of worst-case conditions. The parametersincluded are common to popular designs and typicalapplications.Available device and package combinations can be found in: 7 Series FPGAs Overview (DS180) Defense-Grade 7 Series FPGAs Overview (DS185)This Virtex-7 T and XT FPGA data sheet, part of an overallset of documentation on the 7 series FPGAs, is available onthe Xilinx website at www.xilinx.com/7.DC CharacteristicsTable 1: Absolute Maximum Ratings(1)SymbolDescriptionMinMaxUnitsFPGA LogicVCCINTInternal supply voltage–0.51.1VVCCAUXAuxiliary supply voltage–0.52.0VVCCBRAMSupply voltage for the block RAM memories–0.51.1VOutput drivers supply voltage for 3.3V HR I/O banks–0.53.6VOutput drivers supply voltage for 1.8V HP I/O banks–0.52.0VVCCAUX IOAuxiliary supply voltage–0.52.06VVREFInput reference voltage–0.52.0VI/O input voltage for 3.3V HR I/O banks–0.40VCCO 0.55VI/O input voltage for 1.8V HP I/O banks–0.55VCCO 0.55VI/O input voltage (when VCCO 3.3V) for VREF and differential I/O standards exceptTMDS 33(5)–0.402.625VKey memory battery backup supply–0.52.0VVCCOVIN(2)(3)(4)VCCBATTGTX and GTH TransceiversVMGTAVCCAnalog supply voltage for the GTX/GTH transmitter and receiver circuits–0.51.1VVMGTAVTTAnalog supply voltage for the GTX/GTH transmitter and receiver termination circuits–0.51.32VVMGTVCCAUXAuxiliary analog Quad PLL (QPLL) voltage supply for the GTX/GTH transceivers–0.51.935VVMGTREFCLKGTX/GTH transceiver reference clock absolute input voltage–0.51.32V 2011–2021 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in theUnited States and other countries. All other trademarks are the property of their respective owners.DS183 (v1.29) March 23, 2021Product Specificationwww.xilinx.comSend Feedback1

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 1: Absolute Maximum Ratings(1) Analog supply voltage for the resistor calibration circuit of the GTX/GTH transceivercolumn–0.51.32VVINReceiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage–0.51.26VIDCIN-FLOATDC input current for receiver input pins DC coupled RX termination floating–14mAIDCIN-MGTAVTTDC input current for receiver input pins DC coupled RX termination VMGTAVTT–12mAIDCIN-GNDDC input current for receiver input pins DC coupled RX termination GND–6.5mAIDCOUT-FLOATDC output current for transmitter pins DC coupled RX termination floating–14mA–12mAIDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination VMGTAVTTXADCVCCADCXADC supply relative to GNDADC–0.52.0VVREFPXADC reference input relative to GNDADC–0.52.0VStorage temperature (ambient)–65150 C– 220 C– 260 C– 125 CTemperatureTSTGTSOLMaximum soldering temperature for Pb/Sn component bodies(6)Maximum soldering temperature for Pb-free componentMaximum .Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.The lower absolute voltage specification always applies.For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471).The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5.See Table 10 for TMDS 33 specifications.For soldering guidelines and thermal considerations, see the 7 Series FPGA Packaging and Pinout Specification (UG475).Table 2: Recommended Operating ernal supply voltage0.971.001.03VInternal supply voltage for -1C devices with voltage identification (VID) bitprogrammed to run at 0.9V typical(4).0.870.900.93VFPGA LogicVCCINT(3)Block RAM supply voltage0.971.001.03VVCCBRAM(3)Block RAM supply voltage for -1C devices with voltage identification (VID)bit programmed to run at 0.9V typical(4).0.870.901.03VVCCAUXAuxiliary supply voltage1.711.801.89VSupply voltage for 3.3V HR I/O banks1.14–3.465VSupply voltage for 1.8V HP I/O banks1.14–1.89VAuxiliary supply voltage when set to 1.8V1.711.801.89VAuxiliary supply voltage when set to 2.0V1.942.002.06VVCCO(5)(6)VCCAUX IO(7)I/O input voltage–0.20–VCCO 0.2VVIN(8)I/O input voltage (when VCCO 3.3V) for VREF and differential I/Ostandards except TMDS 33(9)–0.20–2.625VIIN(10)Maximum current through any pin in a powered or unpowered bank whenforward biasing the clamp diode.––10mADS183 (v1.29) March 23, 2021Product Specificationwww.xilinx.comSend Feedback2

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 2: Recommended Operating Conditions(1)(2) 9VAnalog supply voltage for the GTX/GTH transceiver QPLL frequency range 10.3125 GHz(13)(14)0.971.01.08VAnalog supply voltage for the GTX/GTH transceiver QPLL frequency range 10.3125 GHz1.021.051.08VVMGTAVTT(12)Analog supply voltage for the GTX/GTH transmitter and receivertermination circuits1.171.21.23VVMGTVCCAUX(12)Auxiliary analog Quad PLL (QPLL) voltage supply for the transceivers1.751.801.85VVMGTAVTTRCAL(12)Analog supply voltage for the resistor calibration circuit of the GTX/GTHtransceiver column1.171.21.23VVCCADCXADC supply relative to GNDADC1.711.801.89VVREFPExternally supplied reference voltage1.201.251.30VJunction temperature operating range for commercial (C) temperaturedevices0–85 CJunction temperature operating range for extended (E) temperaturedevices0–100 CJunction temperature operating range for industrial (I) temperature devices–40–100 CJunction temperature operating range for military (M) temperature devices–55–125 CVCCBATT(11)Battery voltageGTX and GTH .3.4.5.6.7.8.9.10.11.12.13.14.All voltages are relative to ground.For the design of the power distribution system, consult the 7 Series FPGAs PCB Design and Pin Planning Guide (UG483).VCCINT and VCCBRAM should be connected to the same supply.For more information on the VID bit see the Lowering Power using the Voltage Identification Bit application note (XAPP555).Configuration data is retained even if VCCO drops to 0V.Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HR I/O only), 3.3V (HR I/O only) at 5%.For more information, refer to the VCCAUX IO section of 7 Series FPGAs SelectIO Resources User Guide (UG471).The lower absolute voltage specification always applies.See Table 10 for TMDS 33 specifications.A total of 200 mA per bank should not be exceeded.VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX.Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTX/GTH Transceiver User Guide (UG476).For data rates 10.3125 Gb/s, VMGTAVCC should be 1.0V 3% for lower power consumption.For lower power consumption, VMGTAVCC should be 1.0V 3% over the entire CPLL frequency range.Table 3: DC Characteristics Over Recommended Operating Data retention VCCINT voltage (below which configuration data might be lost)0.75––VVDRIData retention VCCAUX voltage (below which configuration data might be lost)1.5––VIREFVREF leakage current per pin––15µAILInput or output leakage current per pin (sample-tested)––15µACIN(2)Die input capacitance at the pad––8pFDS183 (v1.29) March 23, 2021Product Specificationwww.xilinx.comSend Feedback3

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 3: DC Characteristics Over Recommended Operating Conditions (Cont’d)MinTyp(1)MaxUnitsPad pull-up (when selected) @ VIN 0V, VCCO 3.3V90–330µAPad pull-up (when selected) @ VIN 0V, VCCO 2.5V68–250µAPad pull-up (when selected) @ VIN 0V, VCCO 1.8V34–220µAPad pull-up (when selected) @ VIN 0V, VCCO 1.5V23–150µAPad pull-up (when selected) @ VIN 0V, VCCO 1.2V12–120µAPad pull-down (when selected) @ VIN 3.3V68–330µAPad pull-down (when selected) @ VIN 1.8V45–180µAICCADCAnalog supply current, analog circuits in powered up state––25mAIBATT(3)Battery supply current––150nAThevenin equivalent resistance of programmable input termination to VCCO/2(UNTUNED SPLIT 40)284055 Thevenin equivalent resistance of programmable input termination to VCCO/2(UNTUNED SPLIT 50)355065 Thevenin equivalent resistance of programmable input termination to VCCO/2(UNTUNED SPLIT 60)446083 nTemperature diode ideality factor–1.010––rTemperature diode series resistance–2– SymbolIRPUIRPDRIN TERM(4)DescriptionNotes:1.2.3.4.Typical values are specified at nominal voltage, 25 C.This measurement represents the die capacitance at the pad, not including the package.Maximum value specified for worst-case process at 25 C. For the XC7VX1140T and XC7V2000T devices, multiply the value by the numberof super-logic regions (SLRs) in the device.Termination resistance to a VCCO/2 level.Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for 3.3V HR I/O Banks(1)(2)AC Voltage OvershootVCCO 0.55% of UI @–55 C to 125 CAC Voltage Undershoot% of UI @–55 C to 125 O 0.6046.6–0.604.77VCCO 0.6521.2–0.652.10VCCO 0.709.75–0.700.94VCCO 0.754.55–0.750.43VCCO 0.802.15–0.800.20VCCO 0.851.02–0.850.09VCCO 0.900.49–0.900.04VCCO 0.950.24–0.950.02Notes:1.2.A total of 200 mA per bank should not be exceeded.The peak voltage of the overshoot or undershoot, and the duration above VCCO 0.20V or below GND – 0.20V, must not exceed the valuesin this table.DS183 (v1.29) March 23, 2021Product Specificationwww.xilinx.comSend Feedback4

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for 1.8V HP I/O Banks(1)(2)AC Voltage Overshoot% of UI @–55 C to 125 CAC Voltage Undershoot% of UI @–55 C to 125 CVCCO 0.55100–0.55100VCCO 0.6050.0(3)–0.6050.0(3)VCCO 0.6550.0(3)–0.6550.0(3)VCCO 0.7047.0–0.7050.0(3)VCCO 0.7521.2–0.7550.0(3)VCCO 0.809.71–0.8050.0(3)VCCO 0.854.51–0.8528.4VCCO 0.902.12–0.9012.7VCCO 0.951.01–0.955.79Notes:1.2.3.A total of 200 mA per bank should not be exceeded.The peak voltage of the overshoot or undershoot, and the duration above VCCO 0.20V or below GND – 0.20V, must not exceed the valuesin this table.For UI lasting less than 20 µs.Table 6: Typical Quiescent Supply CurrentSymbolICCINTQDescriptionQuiescent VCCINT supply currentDS183 (v1.29) March 23, 2021Product SpecificationSpeed linx.comSend Feedback5

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 6: Typical Quiescent Supply Current (Cont’d)SymbolICCOQICCAUXQDescriptionQuiescent VCCO supply currentQuiescent VCCAUX supply currentDS183 (v1.29) March 23, 2021Product SpecificationSpeed 183183N/AmAwww.xilinx.comSend Feedback6

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 6: Typical Quiescent Supply Current (Cont’d)SymbolICCAUX IOQICCBRAMQDescriptionQuiescent VCCAUX IO supply currentQuiescent VCCBRAM supply currentSpeed /AN/AN/A6565N/AmANotes:1.2.3.Typical values are specified at nominal voltage, 85 C junction temperatures (Tj) with single-ended SelectIO resources.Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state andfloating.Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to estimate static power consumption forconditions other than those specified.DS183 (v1.29) March 23, 2021Product Specificationwww.xilinx.comSend Feedback7

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsPower‐On/Off Power Supply SequencingThe recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX IO, and VCCO to achieve minimum current drawand ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-onsequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supplyand ramped simultaneously. If VCCAUX, VCCAUX IO, and VCCO have the same recommended voltage levels then they can bepowered by the same supply and ramped simultaneously.For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0: The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for eachpower-on/off cycle to maintain device reliability levels. The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.The recommended power-on sequence to achieve minimum current draw for the GTX/GTH transceivers is VCCINT, VMGTAVCC,VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINTcan be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieveminimum current draw.If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during powerup and power-down. When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT – VMGTAVCC 150 mV and VMGTAVCC 0.7V, the VMGTAVTTcurrent draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can beup to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down. When VMGTAVTT is powered before VCCINT and VMGTAVTT – VCCINT 150 mV and VCCINT 0.7V, the VMGTAVTT currentdraw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down.There is no recommended sequence for supplies not shown.DS183 (v1.29) March 23, 2021Product Specificationwww.xilinx.comSend Feedback8

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 7 shows the minimum current, in addition to ICCQ, that is required by Virtex-7 T and XT devices for proper power-onand configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplieshave passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied.Once initialized and configured, use the Xilinx Power tools to estimate current drain on these supplies.Table 7: Power-On Current for Virtex-7 T and XT DevicesDeviceICCINTMINICCAUXMINICCOMINICCAUX IOICCBRAMUnitsXC7V585TICCINTQ 2700ICCAUXQ 40ICCOQ 60 mA per bankICCOAUXIOQ 40 mA per bank ICCBRAMQ 108mAXC7V2000TICCINTQ 4000ICCAUXQ 80ICCOQ 60 mA per bankICCOAUXIOQ 40 mA per bank ICCBRAMQ 176mAXC7VX330TICCINTQ 1000ICCAUXQ 65ICCOQ 40 mA per bankICCOAUXIOQ 40 mA per bankICCBRAMQ 95mAXC7VX415TICCINTQ 1200ICCAUXQ 75ICCOQ 40 mA per bankICCOAUXIOQ 40 mA per bank ICCBRAMQ 115mAXC7VX485TICCINTQ 1200ICCAUXQ 80ICCOQ 40 mA per bankICCOAUXIOQ 40 mA per bank ICCBRAMQ 140mAXC7VX550TICCINTQ 3300 ICCAUXQ 143 ICCOQ 40 mA per bankICCOAUXIOQ 57 mA per bank ICCBRAMQ 200mAXC7VX690TICCINTQ 3300 ICCAUXQ 143 ICCOQ 40 mA per bankICCOAUXIOQ 57 mA per bank ICCBRAMQ 200mAXC7VX980TICCINTQ 6500 ICCAUXQ 202 ICCOQ 40 mA per bankICCOAUXIOQ 60 mA per bank ICCBRAMQ 204mAXC7VX1140TICCINTQ 8000 ICCAUXQ 235 ICCOQ 40 mA per bankICCOAUXIOQ 63 mA per bank ICCBRAMQ 256mAXQ7V585TICCINTQ 2700ICCAUXQ 40ICCOQ 60 mA per bankICCOAUXIOQ 40 mA per bank ICCBRAMQ 108mAXQ7VX330TICCINTQ 1000ICCAUXQ 65ICCOQ 40 mA per bankICCOAUXIOQ 40 mA per bankICCBRAMQ 95mAXQ7VX485TICCINTQ 1200ICCAUXQ 80ICCOQ 40 mA per bankICCOAUXIOQ 40 mA per bank ICCBRAMQ 140mAXQ7VX690TICCINTQ 3300 ICCAUXQ 143 ICCOQ 40 mA per bankICCOAUXIOQ 57 mA per bank ICCBRAMQ 200mAXQ7VX980TICCINTQ 6500 ICCAUXQ 202 ICCOQ 40 mA per bankICCOAUXIOQ 60 mA per bank ICCBRAMQ 204mATable 8: Power Supply Ramp amp time from GND to 90% of VCCINT0.250msTVCCORamp time from GND to 90% of VCCO0.250msTVCCAUXRamp time from GND to 90% of VCCAUX0.250msTVCCAUX IORamp time from GND to 90% of VCCAUX IO0.250msTVCCBRAMRamp time from GND to 90% of VCCBRAMmsTVCCO2VCCAUXAllowed time per power cycle for VCCO – VCCAUX 2.625V0.250TJ 125 C(1)–300TJ 100 C(1)–50085 C(1)–800TJ msTMGTAVCCRamp time from GND to 90% of VMGTAVCC0.250msTMGTAVTTRamp time from GND to 90% of VMGTAVTT0.250msTMGTVCCAUXRamp time from GND to 90% of VMGTVCCAUX0.250msNotes:1.Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V.DS183 (v1.29) March 23, 2021Product Specificationwww.xilinx.comSend Feedback9

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsDC Input and Output LevelsValues for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommendedoperating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that allstandards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOHvoltage levels shown. Other standards are sample tested.Table 9: SelectIO DC Input and Output Levels(1)(2)I/O StandardVILVIHVOLVOHIOLIOHV, MinV, MaxV, MinV, MaxV, MaxV, MinmAmAHSTL I–0.300VREF – 0.100VREF 0.100VCCO 0.3000.400VCCO – 0.4008–8HSTL I 12–0.300VREF – 0.080VREF 0.080VCCO 0.30025% VCCO75% VCCO6.3–6.3HSTL I 18–0.300VREF – 0.100VREF 0.100VCCO 0.3000.400VCCO – 0.4008–8HSTL II–0.300VREF – 0.100VREF 0.100VCCO 0.3000.400VCCO – 0.40016–16HSTL II 18–0.300VREF – 0.100VREF 0.100VCCO 0.3000.400VCCO – 0.40016–16HSUL 12–0.300VREF – 0.130VREF 0.130VCCO 0.30020% VCCO80% VCCO0.1–0.1LVCMOS12–0.30035% VCCO65% VCCOVCCO 0.3000.400VCCO – 0.400Note 3Note 3LVCMOS15,LVDCI 15–0.30035% VCCO65% VCCOVCCO 0.30025% VCCO75% VCCONote 4Note 4LVCMOS18,LVDCI 18–0.30035% VCCO65% VCCOVCCO 0.3000.450VCCO – 0.450Note 5Note 5LVCMOS25–0.3000.7001.700VCCO 0.3000.400VCCO – 0.400Note 6Note 6LVCMOS33–0.3000.8002.0003.4500.400VCCO – 0.400Note 6Note 6LVTTL–0.3000.8002.0003.4500.4002.400Note 7Note 7MOBILE DDR–0.30020% VCCO80% VCCOVCCO 0.30010% VCCO90% VCCO0.1–0.1PCI33 3–0.40030% VCCO50% VCCOVCCO 0.50010% VCCO90% VCCO1.5–0.5SSTL12–0.300VREF – 0.100VREF 0.100VCCO 0.300 VCCO/2 – 0.150 VCCO/2 0.15014.25–14.25SSTL135–0.300VREF – 0.090VREF 0.090VCCO 0.300 VCCO/2 – 0.150 VCCO/2 0.15013.0–13.0SSTL135 R–0.300VREF – 0.090VREF 0.090VCCO 0.300 VCCO/2 – 0.150 VCCO/2 0.1508.9–8.9SSTL15–0.300VREF – 0.100VREF 0.100VCCO 0.300 VCCO/2 – 0.175 VCCO/2 0.17513.0–13.0SSTL15 R–0.300VREF – 0.100VREF 0.100VCCO 0.300 VCCO/2 – 0.175 VCCO/2 0.1758.9–8.9SSTL18 I–0.300VREF – 0.125VREF 0.125VCCO 0.300 VCCO/2 – 0.470 VCCO/2 0.4708–8SSTL18 II–0.300VREF – 0.125VREF 0.125VCCO 0.300 VCCO/2 – 0.600 VCCO/2 0.60013.4–13.4Notes:1.2.3.4.5.6.7.8.Tested according to relevant specifications.3.3V and 2.5V standards are only supported in 3.3V I/O banks.Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks.Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks.Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks.Supported drive strengths of 4, 8, 12, or 16 mASupported drive strengths of 4, 8, 12, 16, or 24 mAFor detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471).DS183 (v1.29) March 23, 2021Product Specificationwww.xilinx.comSend Feedback10

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 10: Differential SelectIO DC Input and Output LevelsI/O StandardVICM(1)V, Min V, TypBLVDS 25VID(2)V, MaxVOCM(3)V, Min V, Typ V, MaxVOD(4)V, MinV, TypV, MaxV, Min V, Typ V, MaxNote 50.3001.2001.4250.100–––1.250–MINI LVDS 25 00.4500.600PPDS 1000.2500.400RSDS 000.3500.600TMDS 332.7002.9653.2300.1500.6751.200 VCCO–0.405 VCCO–0.300 VCCO–0.190 0.4000.6000.800Notes:1.2.3.4.5.6.7.VICM is the input common mode voltage.VID is the input differential voltage (Q – Q).VOCM is the output common mode voltage.VOD is the output differential voltage (Q – Q).VOD for BLVDS will vary significantly depending on topology and loading.LVDS 25 is specified in Table 12.LVDS is specified in Table 13.Table 11: Complementary Differential SelectIO DC Input and Output LevelsI/O StandardVICM(1)VID(2)VOL(3)VOH(4)IOLIOHV, MinV, TypV, MaxV, MinV, MaxV, MaxV, MinmA, MaxmA, MinDIFF HSTL 00DIFF HSTL I .00DIFF HSTL 16.00DIFF HSTL II 16.00DIFF HSUL 120.3000.6000.8500.100–20% VCCO80% VCCO0.100–0.100DIFF MOBILE DDR0.3000.9001.4250.100–10% VCCO90% VCCO0.100–0.100DIFF SSTL120.3000.6000.8500.100–(VCCO/2) – 0.150(VCCO/2) 0.15014.25–14.25DIFF SSTL1350.3000.6751.0000.100–(VCCO/2) – 0.150(VCCO/2) 0.15013.0–13.0DIFF SSTL135 R0.3000.6751.0000.100–(VCCO/2) – 0.150(VCCO/2) 0.1508.9–8.9DIFF SSTL150.3000.7501.1250.100–(VCCO/2) – 0.175(VCCO/2) 0.17513.0–13.0DIFF SSTL15 R0.3000.7501.1250.100–(VCCO/2) – 0.175(VCCO/2) 0.1758.9–8.9DIFF SSTL18 I0.3000.9001.4250.100–(VCCO/2) – 0.470(VCCO/2) 0.4708.00–8.00DIFF SSTL18 II0.3000.9001.4250.100–(VCCO/2) – 0.600(VCCO/2) 0.60013.4–13.4Notes:1.2.3.4.VICM is the input common mode voltage.VID is the input differential voltage (Q – Q).VOL is the single-ended low-output voltage.VOH is the single-ended high-output voltage.DS183 (v1.29) March 23, 2021Product Specificationwww.xilinx.comSend Feedback11

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsLVDS DC Specifications (LVDS 25)The LVDS standard is available in the HR I/O banks.Table 12: LVDS 25 DC Specifications(1)SymbolDC CCOSupply voltageVOHOutput High voltage for Q and QRT 100 across Q and Q signals––1.675VVOLOutput Low voltage for Q and QRT 100 across Q and Q signals0.700––VDifferential output voltage(Q – Q), Q High(Q – Q), Q HighRT 100 across Q and Q signals247350600mVVODIFFVOCMOutput common-mode voltageRT 100 across Q and Q signals1.0001.2501.425VDifferential input voltage(Q – Q), Q High(Q – Q), Q High100350600mVVIDIFFVICMInput common-mode voltage0.3001.2001.500VNotes:1.Differential inputs for LVDS 25 can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the7 Series FPGAs SelectIO Resources User Guide (UG471) for more information.LVDS DC Specifications (LVDS)The LVDS standard is available in the HP I/O banks.Table 13: LVDS DC SpecificationsSymbolDC CCOSupply voltageVOHOutput High voltage for Q and QRT 100 across Q and Q signals––1.675VVOLOutput Low voltage for Q and QRT 100 across Q and Q signals0.825––VDifferential output voltage(Q – Q), Q High(Q – Q), Q HighRT 100 across Q and Q signals247350600mVVODIFFVOCMOutput common-mode voltageRT 100 across Q and Q signals1.0001.2501.425VDifferential input voltage(Q – Q), Q High(Q – Q), Q HighCommon-mode input voltage 1.25V100350600mVVIDIFFVICMInput common-mode voltageDifferential input voltage 350 mV0.3001.2001.425VNotes:1.Differential inputs for LVDS can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the 7 SeriesFPGAs SelectIO Resources User Guide (UG471) for more information.DS183 (v1.29) March 23, 2021Product Specificationwww.xilinx.comSend Feedback12

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsAC Switching CharacteristicsAll values represented in this data sheet are based on the speed specifications in the ISE Design Suite 14.7 andVivado Design Suite 2013.4 as outlined in Table 14.Table 14: Virtex-7 T and XT FPGA Speed Specification Version By DeviceVersion In:Typical VCCINTDeviceISE 14.7Vivado 2013.4(Table 2)1.051.061.0VXQ7V585T, XQ7VX485T1.061.071.0VXQ7VX330T, XQ7VX690T, XQ7VX980T1.101.111.0VXC7V585T, , XC7VX415T, XC7VX550T, XC7VX690T, XC7VX980TN/A1.111.0VXC7VX1140TSwitching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, orProduction. Each designation is defined as follows:Advance Product SpecificationThese specifications are based on simulations only and are typically available soon after device design specifications arefrozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reportingmight still occur.Preliminary Product SpecificationThese specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades withthis designation are intended to give a better indication of the expected performance of production silicon. The probabilityof under-reporting delays is greatly reduced as compared to Advance data.Production Product SpecificationThese specifications are released once enough production silicon of a particular device family member has beencharacterized to provide full correlation between specifications and devices over numerous production lots. There is nounder-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowestspeed grades transition to Production before faster speed grades.Testing of AC Switching CharacteristicsInternal timing parameters are derived from measuring internal test patterns. All AC switching characteristics arerepresentative of worst-case supply voltage and junction temperature conditions.For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer andback-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-7 T and XT FPGAs.DS183 (v1.29) March 23, 2021Product Specificationwww.xilinx.comSend Feedback13

Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching CharacteristicsSpeed Grade DesignationsSince individual family members are produced at different times, the migration from one category to another dependscompletely on the status of the fabrication process for each device. Table 15 correlates the current status of eachVirtex-7 T and XT device on a per speed grade basis.Table 15: Virtex-7 T and XT Device Speed Grade Design

7. For more information, refer to the VCCAUX_IO section of 7 Series FPGAs SelectIO Resources User Guide (UG471). 8. The lower absolute voltage specification always applies. 9. See Table 10 for TMDS_33 specifications. 10. A total of 200 mA per bank should not be exceeded. 11. VCCBATT is required only when using bitstream encryption.