Genesys 2 FPGA Board Reference Manual Overview - Digilentinc

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1300 Henley CourtPullman, WA 99163509.334.6306www.store.digilent.comGenesys 2 FPGA Board Reference ManualRevised August 24, 2017This manual applies to the Genesys 2 rev. FOverviewThe Digilent Genesys 2 board is an advanced, high-performance, ready-to-use digital circuit development platformbased on the latest Kintex-7 Field Programmable Gate Array (FPGA) from Xilinx. With its high-capacity, highspeed FPGA (Xilinx part number XC7K325T-2FFG900C), fast external memories, high-speed digital video ports, andwide expansions options make the Genesys 2 well suited for data and video processing applications. Several builtin peripherals, including Ethernet, audio and USB 2.0, allow a wide range of other applications. The fully-bonded1high-speed FMC HPC connector opens the door to great expansion possibilities.The Kintex-7 FPGA offers more capacity, higher performance, and more resources than the Virtex-5 from the firstgeneration Genesys: 50,950 logic slices (up 7x), each with four 6input LUTs and 8 flip-flopsClose to 16 Mbits of fast block RAM (up 7x)Ten clock management tiles, each with phaselocked loop (PLL)840 DSP slices (up 17x)Internal clock speeds exceeding 450MHzOn-chip analog-to-digital converter (XADC)Up to 10.3125Gbps gigabit transceivers1800Mbps DDR3 data rate with 32-bit datawidthCommercial -2 speed gradeThe Genesys 2.The Genesys 2 also offers an improved collection of ports and peripherals, including: Fully bonded1 400-pin FMCHPC connector USB-UART Bridge 8 user switches, 6 buttons OLED VGA connector Pmod for XADC signals1 Two four-lane DisplayPortconnectors HDMI Sink and HDMI Source 10/100/1000 Ethernet PHY 1GiB 1800Mt/s on-board DDR3 USB 2.0 Host/Device/OTG PHY Digilent Adept USB port forprogramming and data Ten GTX lanes available in the FMCconnector MicroSD card connector Audio codec w/ four 3.5mm jacks Serial Flash Five Pmod ports USB HID Host for mice, keyboardsand USB MSD Host for storageWith the exception of CLK3 BIDIRDOC#: 410-300Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 1 of 31

Genesys 2 FPGA Board Reference ManualThe Genesys 2 can be programmed from various sources, like USB thumb drive, microSD, the on-board non-volatileFlash, or the on-board USB-JTAG programmer circuit.The Genesys 2 is compatible with Xilinx’s new high-performance Vivado Design Suite as well as the ISE toolset.Included in the box is a voucher that unlocks the Design Edition of Vivado that is device-locked to the Genesys 2.This allows designs to be implemented straight out of the box at no additional cost. The Design Edition of Vivadoalso unlocks the Logic Analyzer tool and still includes the ability to create MicroBlaze soft-core 361278Callout1109Component DescriptionCallout11Component Description14FMC HPC15Fan header3USB-UART bridgeUser-USB (bottom) & USB MSD/HID(top)Ethernet RJ-45 10/100/100016VADJ jumper4USB-JTAG bridge17micro SD slot5PROG and user reset buttons183.5mm audio jacks6Power LED19DisplayPort source connector7Digital Pmods20DisplayPort sink connector2Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 2 of 31

Genesys 2 FPGA Board Reference ManualCalloutComponent DescriptionCalloutComponent Description8JTAG header21VGA connector9User slide switches22HDMI source connector10User LEDs23FPGA configuration source jumper11OLED display24HDMI sink connector12Dual analog/digital Pmod25Power switch13User pushbuttons26Power jack 12VDCTable 1. Genesys 2 features and connectors1Quick-startThe Genesys 2 comes with an out-of-box demo design that gets loaded from the on-board QSPI flash. It exercisesmost of the on-board peripherals. Just power the board with the included 12V wall supply, flick the power switch,wait for the design to fully load, and explore the following features: Connecting an HDMI/DVI, VGA, or DisplayPort monitor shows a demo image with a mouse pointer.Connecting a USB mouse controls the mouse pointer on the display.The OLED shows the Digilent logo and various information on several pages. Advance between pages withthe BTNC button.The internal FPGA temperature, voltage and current readings of various power rails are shown on theOLED.Connecting the board to an Ethernet network will acquire link, IP address and become “pingable” at theIPv4 address displayed on the OLED.Connecting the USB-UART port to a PC and opening a terminal (115200, 8, N, 1) shows status messages.Pushing BTNU records audio off the microphone input for five seconds and plays it back on theheadphone output if BTND is pushed, or line-out if BTNL. Similarly, BTNR starts a recording off the line-injack.The LEDs are showing a scanning light bar.The fan starts when FPGA internal temperature reaches 60 C and stops when it drops back to 40 C.To develop new FPGA designs for the Genesys 2, download and install the Xilinx Vivado Design Suite2. The toolsinclude all the USB drivers for the board. Once installed, the USB JTAG and USB UART ports can be connected tothe PC and making the FPGA visible in Vivado Hardware Manager.Additional resources can be found on the Genesys 2 Resource Center.2Power SuppliesThe Genesys 2 board can receive power from an external power supply through the center-positive barrel jack(J27). The external supply voltage must be 12 V 5 %. The Genesys 2 cannot be powered from the USB ivado.htmlCopyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 3 of 31

Genesys 2 FPGA Board Reference ManualAll Genesys 2 power supplies can be turned on and off together by a single logic-level power switch (SW8). Powersupplies are either enabled/disabled directly by the power switch or indirectly by other supplies upstream. Apower-good LED (LD15), driven by the “power good” output of the on-board regulators, indicates that the suppliesare turned on and operating normally. An overview of the Genesys 2 power circuit is shown in Figure 1.12V Power Jack(J27)Power Switch(SW8)VCC1V8 (5A)LTC3605MGTAVTT1V2 (1.5A)LTC3026VCC1V0 (14A)LTC3866MGTAVCC1V0 (2A)LT3083VCC3V3 (6A)LTC3855#1VCCAUXIO2V0 ( 150mA)LT1762VCC5V0 (3A)LTC3855#2VCC1V5 (2A)LTC3618#1VADJ (5A)LTM4618VTT0V75 (2A)LTC3618#2VSWT12V0 (1A)MGTAVCCAUX1V8 (100mA)LT1762VCCADC (100mA)LT1761VREFP1V25 (25mA)LT1790VCCAVDD3V3 (100mA)LT1761VREF0V75 (10mA)LT3618#3Figure 1. Genesys 2 power circuitAn external power supply can be used by plugging it into the power jack (J27). The supply must use a coax, centerpositive 2.1mm internal-diameter plug, and deliver 12VDC 5 %. The minimum current rating of the supplydepends on the actual design implemented in the FPGA, but at least 3A (i.e., at least 36W) is recommended. Forhigh-power FMC applications, a 60W supply is recommended.Voltage regulator circuits from Linear Technology create the different voltages required by the FPGA and on-boardperipherals from the main power input. Some regulators use the outputs of another regulator as input, dependingon design considerations. In some cases, this chaining helps in creating the proper power-on sequence for circuits.In other cases, the chaining of power supply enables achieves the same purpose.Table 2 provides information on maximum and typical currents for each power rail. The typical currents stronglydepend on FPGA configuration and the values provided are the current consumption of the OOB demo.Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 4 of 31

Genesys 2 FPGA Board Reference ManualSupplyCircuitsDeviceCurrent (max/typical)3.3 VFPGA I/O, USB, FMC, Clocks,Pmod, Ethernet, SD slot,Flash, DisplayPort, HDMIIC42: LTC3855#16 A / 0.8 A1.0 VFPGA CoreIC30: LTC386614 A / 1.2 A1.8 VFPGA AuxiliaryIC36: LTC36055 A / 1.6 A1.5 VDDR3 and FPGA I/OIC32: LTC36182 A / 0.7 A0.75VDDR3 termination, referenceIC32: LTC36182A2.0 VFPGA Auxiliary I/O formemory high data rates3IC38: LT1762150 mAVADJ(1.2-3.3 V)User I/O, FMC and FPGA I/OIC37: LTM46185A3.3 VAudio analog supplyIC12: LT1761100 mA5.0 VUSB Host, HDMIIC42: LTC3855#23 A / 0.3 AMGT 1.0 VGigabit Transceivers VCCIC41: LT30832AMGT 1.2 VGigabit Transceivers VTTIC39: LTC30261.5 AMGT 1.8 VGigabit Transceivers AUXIC40: LT1762150 mAXADC 1.8 VXADC supplyIC47: LT1761100 mAXADC 1.25 VXADC referenceIC48: LT17905 mATable 2. Voltage rail power ratings.The VADJ power rail requires special attention. It is an adjustable rail that powers the FMC mezzanine connector,user push-buttons, switches, XADC Pmod connector and the FPGA banks connected to these peripherals (banks 15,16, 17). The feedback pin of the VADJ regulator is connected to a resistor network modifiable by jumper JP6.Changing its position changes the resistor divider in the feedback loop, thereby changing the voltage on theregulator’s output. The possible voltages are listed in Figure 2. If JP6 is not set, the VADJ voltage defaults to 1.2 V.This feature enables setting the VADJ voltage to suit a certain FMC mezzanine card or application. It isrecommended to only change the JP6 position with the power switch in the OFF position.Please note that for proper voltage levels in digital signals connected to V ADJ-powered FPGA banks (ex. user pushbuttons), the correct I/O standard still needs to be set in the design user constraints (XDC or UCF file). See theschematic and/or the constraints file to determine which signals are in V ADJ-powered banks. The provided masterUCF and XDC files assume the default VADJ voltage of 1.2V, declaring LVCMOS12 as the I/O standard for thesesignals.JP6JP6JP6JP6VADJ 1.2VVADJ 1.8VVADJ 2.5VVADJ 3.3VFigure 2. VADJ programmable voltages.3See the 7 Series FPGAs SelectIO Resources User Guide (ug471) for details.Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 5 of 31

Genesys 2 FPGA Board Reference Manual3Power monitoringI2C-interfaced monitoring circuits, INA219 from Texas Instruments, are available on the main power rails. These allow real-time voltage, current,and power readings in the FPGA. Six such circuits share the same I2C bus with different slave addresses. These are summarized inTable 3, along with recommended configuration 0I2C 100b1000000ShuntresistorConfigurationregister5 33IC35IC34IC44IC46Table 3. Power monitoring circuit parameters.The configuration and calibration registers are volatile, so they need to be initialized after power-up. Afterinitialization is done voltage, current, and power values can be read from dedicated registers. It is recommendedto add glitch filters to the I2C master controller to avoid spurious start or stop conditions occurring on the bus. Thisis especially important when using an external I2C master connected to the J18 header (not mounted by default).For more information on the INA219, see its datasheet 4.The principle of operation is measuring bus and shunt voltages using a programmable-gain differential amplifierand an analog-to-digital converter. The schematic for one such circuit is shown in Figure 3. The two analog inputsare connected across a shunt resistor placed in series between the power supply and the load. Current consumedby the load produce a voltage drop across the shunt resistor. This voltage is measured by the INA219 and is used tocalculate the current. In addition, the bus voltage is measured on V- with respect to GND and is the voltage on therespective power rail. The voltage and current measurements are used to calculate power consumption. If theINA219 is configured, it will correctly calculate all three parameters. In its default, power-up configuration itprovides bus and shunt voltage only, which can be used to calculate current and power in the FPGA.Power railOUTVCC3V3V VSDASCLPower supplyAF30AE30INA219Kintex-7Figure 3. Power monitoring circuit4http://www.ti.com/lit/gpn/ina219Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 6 of 31

Genesys 2 FPGA Board Reference Manual4FanThe Genesys 2 comes with a fan and a secondary heat sink pre-installed on the FPGA package heat sink. The fan ispowered from the external 12V DC supply rail and controlled by the FPGA. Control is done by the “FAN EN” signal.Pulling the signal high from the FPGA opens the transistor driving the fan. This pin is pulled high by default.Feedback is obtained on the “FAN TACH” signal. This generates a pulse with a frequency proportional to therotation speed of the fan. Each rotation generates four pulses on “FAN TACH”. The period of these pulses shortenswith higher rotation speed and lengthens at slower speeds.V1 rotation3.3Fan locked0t1 pulseFigure 4. “FAN TACH” fan speed feedback signal.The fan uses a 3-pin header for power, ground and feedback. It is recommended leaving the fan connected at alltimes. Depending on FPGA design complexity and actual usage the fan might not be needed at all. In this case theenable signal can be used to stop the fan, and start it when the FPGA internal temperature (as read by the XADC)gets above a certain limit.5FPGA ConfigurationAfter power-on, the Kintex-7 FPGA must be configured (or programmed) before it can perform any functions. Youcan configure the FPGA in one of four ways:1.2.3.4.A PC can use the Digilent USB-JTAG circuitry (port J17, labeled “USB JTAG”) to program the FPGA any timethe power is on.A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA.A programming file can be transferred to the FPGA from a micro SD card.A programming file can be transferred from a USB mass-storage device (ex. pen drive) attached to theUSB HOST port.Figure 5 shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP5) and amedia selection jumper (JP4) select between the programming modes.Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 7 of 31

Genesys 2 FPGA Board Reference ManualMicro-B USBConnector(J17)6-pin JTAGHeader(J19)USBControllerJTAGPort1x6 JTAGHeaderSPI quad-modeFlashMode (JP5)Kintex-7M0M2M1Micro SDConnector (J3)Type A USBHostConnector(J7-top)SPIPortUser I/ODONE2PIC24SlaveSerialPROG BJP4JP5anyFlashanyJTAGUSBmicroSDProgramming ModeMedia Select (JP4)Figure 5. Genesys 2 Configuration Options.The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivadosoftware from Xilinx can create bitstreams from VHDL, Verilog, or schematic-based source files (in the ISE toolset,EDK is used for MicroBlaze embedded processor-based designs).Bitstreams are stored in volatile SRAM-based memory cells within the FPGA. This data defines the FPGA’s logicfunctions and circuit connections, and it remains valid until it is erased by removing board power, by pressing thereset button attached to the PROG input, or by writing a new configuration file using the JTAG port.A Kintex-7 325T bitstream is typically 91,548,896 bits long and can take a long time to transfer depending on theprogramming mode. The time it takes to program the Genesys 2 can be decreased by compressing the bitstreambefore programming, and then allowing the FPGA to decompress the bitstream itself during configuration.Depending on design complexity, compression ratios of 10x can be achieved. Bitstream compression can beenabled within the Xilinx tools (ISE or Vivado) to occur during generation. For instructions on how to do this,consult the Xilinx documentation for the toolset being used. This option is available for all programming modes.Mode-specific speed-ups are also available. JTAG clock frequency can be set to the maximum supported by theprogramming cable in iMPACT/Vivado Hardware Manager. Similarly, the clock frequency for the SPI Flash can beincreased in device properties (Vivado) or bitstream generation options (ISE). The micro-SD and USB mass-storagedevice configuration modes already operate at their maximum possible speed.After being successfully programmed, the FPGA will cause the "DONE" LED (LD14) to illuminate. Pressing the“PROG” button (BTN2) at any time will reset the configuration memory in the FPGA. After being reset, the FPGAwill immediately attempt to reprogram itself from whatever method has been selected by the programming modejumpers.The following sections provide greater detail about programming the Genesys 2 using the different methodsavailable.5.1JTAG ProgrammingThe Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture,commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA usingCopyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 8 of 31

Genesys 2 FPGA Board Reference Manualthe onboard Digilent USB-JTAG circuitry (port J17) or an external JTAG programmer, such as the Digilent JTAG HS2,attached to port J19. You can perform JTAG programming at any time after the Genesys 2 has been powered on,regardless of what the mode jumper (JP5) is set to. If the FPGA is already configured, then the existingconfiguration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAGsetting is useful to prevent the FPGA from being configured from any other bitstream source until a JTAGprogramming occurs.Programming the Genesys 2 with an uncompressed bitstream using the on-board USB JTAG circuitry usually takesaround four seconds with a 30MHz JTAG clock.JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and theLabtools version of Vivado.The demonstration project5 available on the Genesys 2 Resource Center6 provides an in-depth tutorial on how toprogram your board.5.2Quad-SPI ProgrammingFor the FPGA to be able to configure itself from the SPI Flash, it first needs to be programmed with the bitstream.This is called indirect programming and is a two-step process controlled by Hardware Manager (Vivado) or iMPACT(ISE). First, the FPGA is programmed with a design that can program flash devices, and then data is transferred tothe flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). After the flashdevice has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event asdetermined by the mode jumper setting. Programming files stored in the flash device will remain until they areoverwritten, regardless of power-cycle events.Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase processinherent to the memory technology. Once written however, FPGA configuration can be very fast, less than asecond. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx tools thatcan affect configuration speed. The on-board flash has a Quad-SPI interface, which supports single (x1), dual (x2)and quad (x4) modes. The quad mode results in the fastest possible data transfer rate. For it to work, the bitstreamneeds to be generated with the x4 bus width option (Vivado device property) and the non-volatile quadconfiguration bit in the flash to be enabled. The Genesys 2 is shipped with this bit enabled.Indirect programming of the flash can be done using the iMPACT tool included with ISE or Hardware Manager ofVivado. The correct part to be set in the tools is s25fl256xxxxxx0 from the manufacturer Spansion.5.3USB Host and Micro SD ProgrammingYou can program the FPGA from a pen drive attached to the USB-Host port (J7-top row) or a microSD card insertedinto J3 by doing the following:1.2.3.4.5.56Format the storage device (pen drive or microSD card) with a FAT32 file system.Place a single .bit configuration file in the root directory of the storage device.Attach the storage device to the Genesys 2.Set the JP5 Programming Mode jumper on the Genesys 2 to “USB/SD”.Select the desired storage device using programmable-logic/genesys-2/startCopyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 9 of 31

Genesys 2 FPGA Board Reference Manual6.Push the PROG button or power-cycle the Genesys 2.The FPGA will automatically configure with the .bit file on the selected storage device. Any .bit files that are notbuilt for the proper Kintex-7 device will be rejected by the FPGA.The Auxiliary Function Status or “BUSY” LED (LD11) gives visual feedback on the state of the configuration processwhen the FPGA is not yet programmed: When steadily lit the auxiliary microcontroller is either booting up or currently reading the configurationmedium (microSD or pen drive) and downloading a bitstream to the FPGA.A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in.In case of an error during configuration the LED will blink rapidly. It could be that the device plugged in isnot getting recognized, it is not properly formatted or the bitstream is not compatible with the FPGA.When the FPGA has been successfully configured, the behavior of the LED is application-specific. For example, if aUSB keyboard or mouse is plugged in, a rapid short blink will signal the receipt of an HID input report fromperipheral.6MemoryThe Genesys 2 board contains two external memories: a 1GiByte volatile DDR3 memory and a 32MiByte nonvolatile serial Flash device. The DDR3 uses two 16-bit wide memory component with industry-standard interfacesoldered on the board resulting in a 32-bit data bus. The serial Flash is on a dedicated quad-mode (x4) SPI bus.6.1DDR3The Genesys 2 includes two Micron MT41J256M16HA-107 DDR3 memory component creating a single rank, 32-bitwide interface. It is routed to a 1.5V-powered HP (High Performance) FPGA bank with 40 ohm controlled singleended trace impedance. For data signals 40 ohm DCI terminations in the FPGA are used to match the tracecharacteristics. Similarly, on the memory side on-die terminations (ODT) are used for impedance matching.Address/Control signals are terminated using discrete resistors.The highest data rate supported is 1800Mbps.For proper operation of the memory a memory controller and physical layer (PHY) interface needs to be included in the FPGA design. The Xilinx7-series memory interface solutions core generated by the MIG (Memory Interface Generator) Wizard hides away the complexities of a DDR3interface. Depending on the tool used (ISE, EDK or Vivado) the MIG Wizard can generate a native FIFO-style or an AXI4 interface to connect touser logic. This workflow allows the customization of several DDR3 parameters optimized for the particular application.Table 4 below lists the MIG Wizard settings optimized for the Genesys 2.SettingMemory typeMax. clock periodMax. data rateClock ratioVCCAUX IOMemory typeMemory partMemory voltageData widthValueDDR3 SDRAM1112ps ( 900MHz) pyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 10 of 31

Genesys 2 FPGA Board Reference ManualSettingData maskInput clock periodOutput driver impedanceChip Select pinRtt (nominal) – On-die terminationInternal VrefReference clockInternal termination impedanceDCI cascadeValueEnabled5004ps ( 200MHz)RZQ/7EnabledRZQ/6DisabledUse system clockN/ADisabledTable 4. DDR3 Settings for the Genesys 2.The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generatingthe IP core. For your convenience an importable UCF/XDC file is provided on the Digilent website to speed up theprocess.For more details on the Xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface SolutionsUser Guide (ug586)7.6.2Quad-SPI FlashNon-volatile storage is provided by a Spansion S25FL256S flash memory. FPGA configuration files can be written toit, and mode settings are available to cause the FPGA to automatically read a configuration from this device atpower on. A Kintex-7 325T configuration file requires just over 10 MiB (mebibyte) of memory, leaving about 70% ofthe flash device available for user data. Or, if the FPGA is getting configured from another source, the wholememory can be used for custom data.The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementationof this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purposeuser I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even afterconfiguration. Access to this pin is provided through a special FPGA primitive called STARTUPE2. The AXI Quad SPIIP core is recommended for easy access to the Flash memory.NOTE: Refer to the manufacturer’s data sheets8 and Xilinx user guides9 for more tation/ip documentation/mig 7series/v2 1/ug586 7Series S25FL128S 256S /user guides/ug470 7Series Config.pdf8Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 11 of 31

Genesys 2 FPGA Board Reference ManualSPI FlashKintex-7CS#SDI/DQ0SDO/DQ1WP#/DQ2HLD#/DQ3SCK SPI FlashU19P24R25R20R21N/A**SCK Is only available via the STARTUPE2 primitiveFigure 6. Genesys 2 SPI Flash pin-out.7Ethernet PHYThe Genesys 2 board includes a Realtek RTL8211E-VL PHY paired with an RJ-45 Ethernet jack with integratedmagnetics to implement a 10/100/1000 Ethernet port for network connection. The PHY interfaces with the FPGAvia RGMII for data and MDIO for management. Bank 33 powered at 1.5V is populated with these signals. Theauxiliary interrupt (INTB), power management (PMEB) signals are wired to bank 32 and powered at 1.8V. Both ofthese signals are open-drain outputs from the PHY and need internal pull-ups enabled in the FPGA, if they areused. The reset signal (PHYRSTB) is wired to bank 12, powered at 3.3V. The connection diagram can be seen onFigure 7.At power-on reset, the PHY is set to the following defaults using the configuration pins in parenthesis: Auto-negotiation enabled, advertising all 10/100/1000 modes (AN[1:0])PHY address 00001 (PHY AD[2:0])No delay for TXD and RXD relative to TXC and RXC for data latching (RXDLY, TXDLY)If an Ethernet cable is plugged in, establishing link is attempted straight after power-up, even if the FPGA is notprogrammed.Two status indicator LEDs are on-board near the RJ-45 connector that indicate traffic (LD10) and valid link state(LD9). The table below shows the default BlinkingTransmitting or receivingLINKLD9OnLink upBlinking 0.4s ON, 2s OFFLink up, Energy Efficient Ethernet (EEE) modeTable 5. Ethernet status LEDs.The on-board PHY implements Layer 1 in the Ethernet stack, interfacing between the physical copper medium andthe media access control (MAC). The MAC must be implemented in the FPGA and mapped to the PHY’s RGMIIinterface. Vivado-based design can use the Xilinx AXI Ethernet Subsystem IP core to implement the MAC and wireit to the processor and the memory subsystem. At the time of writing the IP core needed to be licensed separately.Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 12 of 31

Genesys 2 FPGA Board Reference ManualOn an Ethernet network each node needs a unique MAC address. To this end the Genesys 2 comes with a MACaddress pre-programmed in a special one-time programmable region (OTP Region 1) of the Quad-SPI Flash8. Thisunique identifier can be read with the OTP Read command (0x4B). The out-of-box Ethernet demo uses the uniqueMAC to allow connecting several Genesys 2 boards to the same network.A downloadable demonstration project can be found on the Genesys 2 Resource /SELRGVRXD1/TXDLYRXD2/AN0RXD3/AN1RXCTL/PHY LTXCAK16AH24INTBPHYRSTBRJ-45 withmagnetics8ACT LED (LD10)LED0/PHY AD0LED1/PHY AD125 MHzCrystalKintex-7LINK LED(LD9)CKXTAL1CKXTAL2Realtek RTL8211E*Bootstrapping pull-ups and pull-downs not included. See Genesys 2 Schematic insteadFigure 7. Pin connections between the FPGA and the Ethernet PHY.8Oscillators/ClocksThe Genesys 2 board includes several oscillators and crystals, of which two are connected to the FPGA. Onedifferential LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. This input clock candrive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may beneeded throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz inputCopyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 13 of 31

Genesys 2 FPGA Board Reference Manualclock. For a full description of these rules and of the capabilities of the Kintex-7 clocking resources, refer to the “7Series FPGAs Clocking Resources User Guide” (ug47210) available from Xilinx.Xilinx offers the

based on the latest Kintex-7 Field Programmable Gate Array (FPGA) from Xilinx. With its high-capacity, high- . The Kintex-7 FPGA offers more capacity, higher performance, and more resources than the Virtex-5 from the first- . 3 See the 7 Series FPGAs SelectIO Resources User Guide (ug471) for details. Genesys 2 FPGA Board Reference Manual